Renesas Laptop 6NM 用户手册

Rev.1.10 Jul 01, 2005 page 172 of 318
REJ09B0124-0110

M16C/6N Group (M16C/6NK, M16C/6NM)

14. Serial I/O

Under development

This document is under development and its contents are subject to change.

Figure 14.32 Transmit and Receive Timing in SIM Mode

The above timing diagram applies to the case where data is
received in the direct format.

STPS bit in U2MR register = 0 (1 stop bit)
PRY bit in U2MR register = 1 (even parity)
UFORM bit in U2C0 register = 0 (LSB first)
U2LCH bit in U2C1 register = 0 (no reverse)
U2IRS bit in U2C1 register = 1 (transmit is completed)

Transfer clock

An "L" level is output from TXD2 due to
the occurrence of a parity error

Read the U2RB register

Set to "0" by an interrupt request acknowledgement or a program

D0 D1 D2 D3 D4 D5 D6 D7

TXD2

D0 D1 D2 D3 D4 D5 D6 D7

TXD2

RXD2 pin level

(1)

Parity error signal sent
back from receiving end

Start

bit

Parity

bit

Stop
bit

Write data to U2TB register

Transferred from U2TB register to UART2 transmit register

An "L" level returns due to the
occurrence of a parity error.

The level is
detected by the
interrupt routine.

The level is detected by the
interrupt routine.

The IR bit is set to "1" at the
falling edge of transfer clock

TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT

fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG

TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT

fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG

The above timing diagram applies to the case where data is
transferred in the direct format.

Start

bit

Parity

bit

Stop
bit

Set to "0" by an interrupt request acknowledgement or a program

Read the U2RB register

Transfer clock

Transmit waveform

from transmitting end

(1) Transmission

(2) Reception

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

NOTE:

1. Because TXD2 and RXD2 are connected, a composite waveform, consisting of transmit waveform from the transmitting end and

parity error signal from receiving end, is generated.

NOTE:

1. Because TXD2 and RXD2 are connected, a composite waveform, consisting of the TXD2 output and the parity error signal sent back