Fujitsu MB15C101 数据表
6
MB15C101
■
FUNCTIONAL DESCRIPTIONS
Two different frequencies can be selected by Div input “H” or “L”.
The divide ratios are calculated using the following equation:
The divide ratios are calculated using the following equation:
f
VCO
= {(P
×
N) + A}
×
f
OSC
÷
R (A < N)
■
PHASE DETECTOR TIME CHART
Note: • .Phase error detection range: –2
π
to +2
π
• Pulses on Do output signal during locked state are output to prevent dead zone.
• LD output becomes low when phase is t
• LD output becomes low when phase is t
WU
or more. LD output becomes high when phase error is t
WL
or
less and continues to be so for three cycles or more.
• .t
WU
and t
WL
depend on OSCin input frequency.
t
WU
> 8/fosc (s) (e. g.t
WU
> 625.0ns, foscin = 12.8 MHz)
t
WL
< 16/fosc (s) (e. g. t
WL
< 1250.0ns, foscin = 12.8 MHz)
Symbol
Description
Div = “H”
Div = “L”
fvco
Output frequency of external VCO
233.15 MHz
259.20 MHz
fosc
Reference oscillation frequency
19.2 MHz
19.2 MHz
N
Divide ratio of the main counter
291
33
A
Divide ratio of the swallow counter
7
12
P
Preset divide ratio of dual modulus
prescaler
16/17
16/17
R
Divide ratio of the reference counter
384 (fr = 50 kHz)
40 (fr = 480 kHz)
fr
fp
LD
D
O
High impedance
t
WL
t
WU