Maxim MAX9850 数据表

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页码 2
Figure 2 shows digital audio data formatted using the I
2
S standard. I
2
S-formatted digital audio is identified by the
MSB of the data word clocked into the decoder on the second BCLK pulse following an LRCLK transition. Figure 2
shows two channels of audio data being clocked into the decoder. Both channels have the MSB delayed by one
BCLK cycle.
This delay is the main difference between I
2
S and left-justified digital audio formats.
Work Around:
Left-justified audio mode must be used instead of I
2
S mode.
Most µP/µC/DSPs have a register(s) that controls how the digital audio data is formatted. The formats may not
use the same naming convention as similar parts, but figures showing the data timing or frame format can be
used to determine which mode needs to be used for proper MAX9850 operation.
For example, the Freescale SCF5250 microprocessor uses a digital audio interface that can operate in two
modes. They call these modes IIS (I
2
S) mode and Sony EIAJ mode (left justified).
The user’s manual for the part can be found here
http://www.freescale.com/files/platforms/doc/user_guide/SCF5250_USERS_MANUAL.pdf
Page 17-5 details the three digital audio interface registers. Tables 17-4 to 17-7 detail the configuration registers
and bit descriptions.
The bit named MODE (bit 5) allows the user to toggle between the two modes.
Figure 17-2 on page 17-10 is a graphical representation of the two modes (IIS and EIAJ). This figure can be used
to compare the format to the MAX9850 data sheet to see that EIAJ mode (from the Freescale data sheet) and left-
justified mode (from the MAX9850 data sheet) are the same.
MAX9850 ERRATA SHEET
2 of 2
0 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
LEFT DATA SAMPLE
LEFT DATA SAMPLE
LRCLK(OUT)
SDIN
BCLK(OUT)
SDOUT
RIGHT
RIGHT DATA SAMPLE
RIGHT DATA SAMPLE
LEFT
MASTER MODE: S_WCI = 0, S_BCI = 0, S_DLY = 0, S_WS = 0
Figure 2. I
2
S-Formatted Digital Audio Data