Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 用户手册
产品代码
BX80605X3430
Processor Integrated I/O (IIO) Configuration Registers
48
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
3.3.3.25
PMBASEU—Prefetchable Memory Base (Upper 32 bits)
The Prefetchable Base Upper 32-bits and Prefetchable Limit Upper 32-bits registers are
extensions to the Prefetchable Memory Base and Prefetchable Memory Limit registers
to support a 64-bit prefetchable memory address range.
extensions to the Prefetchable Memory Base and Prefetchable Memory Limit registers
to support a 64-bit prefetchable memory address range.
3.3.3.26
PMLIMITU—Prefetchable Memory Limit (Upper 32 bits)
3.3.3.27
BCTRL—Bridge Control Register
The Bridge Control register provides additional control for the secondary interface (that
is, PCI Express) as well as some bits that affect the overall behavior of the “virtual”
PCI-to-PCI bridge embedded within the Integrated I/O, for example, VGA-compatible
address range mapping.
is, PCI Express) as well as some bits that affect the overall behavior of the “virtual”
PCI-to-PCI bridge embedded within the Integrated I/O, for example, VGA-compatible
address range mapping.
Register:
PMBASEU
Device: 3-6
(PCIe)
Function: 0
Offset:
28h
Bit
Attr
Default
Description
31:0
RW
00000000h
Prefetchable Upper 32-bit Memory Base Address
Corresponds to A[63:32] of the memory address that maps to the upper base
Corresponds to A[63:32] of the memory address that maps to the upper base
of the prefetchable range of memory accesses that will be passed by the PCI
Express bridge. The OS should program these bits based on the available
physical limits of the system.
Register:
PMLIMITU
Device: 3-6
(PCIe)
Function: 0
Offset:
2Ch
Bit
Attr
Default
Description
31:0
RW
00000000h
Prefetchable Upper 32-bit Memory Limit Address
Corresponds to A[63:32] of the memory address that maps to the upper limit
Corresponds to A[63:32] of the memory address that maps to the upper limit
of the prefetchable range of memory accesses that will be passed by the PCI
Express bridge. OS should program these bits based on the available physical
limits of the system.
(Sheet 1 of 2)
Register:
BCTRL
Device: 3-6
(PCIe)
Function: 0
Offset:
3Eh
Bit
Attr
Default
Description
15:12
RO
0h
Reserved
11
RO
0
Discard Timer SERR Status
Not applicable to PCI Express*. This bit is hardwired to 0.
Not applicable to PCI Express*. This bit is hardwired to 0.
10
RO
0
Discard Timer Status
Not applicable to PCI Express. This bit is hardwired to 0.
Not applicable to PCI Express. This bit is hardwired to 0.
9
RO
0
Secondary Discard Timer
Not applicable to PCI Express. This bit is hardwired to 0.
Not applicable to PCI Express. This bit is hardwired to 0.
8
RO
0
Primary Discard Timer
Not applicable to PCI Express. This bit is hardwired to 0.
Not applicable to PCI Express. This bit is hardwired to 0.