Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 用户手册

Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

51

This is the base address for the root complex configuration space. This window of 
addresses contains the Root complex Register set for the PCI Express hierarchy 
associated with the processor. On Reset, the Root complex configuration space is 
disabled and must be enabled by writing a 1 to DMIRCBAREN [Device 0, offset 50h, 
bit0]. All the bits in this register are locked in Intel TXT enabled mode.

31:12

RWO

00000h

DMI Base Address (DMIRCBAR) 
This field corresponds to Bits 32:12 of the base address DMI Root Complex 

register space. BIOS will program this register resulting in a base address for a 

4-KB block of contiguous memory address space. This register ensures that a 

naturally aligned 4-KB space is allocated within the first 64 GB of addressable 

memory space. System Software uses this base address to program the DMI 

Root Complex register set. All the Bits in this register are locked in Intel 

Trusted Execution Technology (Intel TXT) enabled mode.

11:1

RV

00h

Reserved 

0

RW

0

DMIRCBAR Enable (DMIRCBAREN)
0 = DMIRCBAR is disabled and does not claim any memory.

1 = DMIRCBAR memory mapped accesses are claimed and decoded.

7:0

RO

05h 

Capability Identifier
Assigned by PCI-SIG for MSI (root ports).

7:0

RWO

90h

Next Ptr
This field is set to 90h for the next capability list (PCI Express capability 

structure) in the chain.