Fujitsu MHV2080BH 用户手册
5.2 Logical Interface
C141-E224
5-27
(8) Status
field
The contents of this field indicate the status of the device. The contents of this
field are updated at the completion of each command. When the BSY bit is 1,
other bits of this field, are invalid.
field are updated at the completion of each command. When the BSY bit is 1,
other bits of this field, are invalid.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BSY DRDY DF DSC DRQ
0
0
ERR
- Bit 7:
Busy (BSY) bit.
This bit is set whenever the Command filed of the shadow block registers for the
host system is accessed.
host system is accessed.
Then this bit is cleared when the command is completed. However, even if a
command is being executed, this bit is cleared during the PIO data transfer request.
command is being executed, this bit is cleared during the PIO data transfer request.
When BSY bit is 1, the host system should not write the shadow block registers.
This bit is set by the device under following conditions:
This bit is set by the device under following conditions:
(a) After COMRESET or SRST is set in the Device Control Field, the BSY bit is
set, then the BSY bit is cleared, when the COMRESET process is completed.
The BSY bit is set for no longer than 15 seconds after the IDD accepts reset.
- Bit 6:
Device Ready (DRDY) bit.
This bit indicates that the device is capable to respond to a command.
The IDD checks its status when it receives a command. If an error is detected (not
ready state), the IDD clears this bit to 0. This is cleared to 0 at power-on and it is
cleared until the rotational speed of the spindle motor reaches the steady speed.
ready state), the IDD clears this bit to 0. This is cleared to 0 at power-on and it is
cleared until the rotational speed of the spindle motor reaches the steady speed.
- Bit 5:
Device Write Fault (DF) bit.
This bit indicates that a device fault (write fault) condition has been detected.
If a write fault is detected during command execution, this bit is latched and
retained until the device accepts the next command or reset.
retained until the device accepts the next command or reset.
- Bit 4:
Device Seek Complete (DSC) bit.
This bit indicates that the device heads are positioned over a track.
In the IDD, this bit is always set to 1 after the spin-up control is completed.
- Bit 3:
Data Request (DRQ) bit.
This bit indicates that the device is ready to transfer PIO data of word unit or byte
unit between the host system and the device.
unit between the host system and the device.
- Bit 2:
Always 0.
- Bit 1:
Always 0.
- Bit 0:
Error (ERR) bit.
This bit indicates that an error was detected while the previous command was
being executed. The Error field indicates the additional information of the cause
for the error.
being executed. The Error field indicates the additional information of the cause
for the error.