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4.7
Event-Trigger Submodule Registers
Event-Trigger Submodule Registers
Figure 4-21. Trip-Zone Clear Register (TZCLR)
15
8
Reserved
R-0
7
3
2
1
0
Reserved
OST
CBC
INT
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-21. Trip-Zone Clear Register (TZCLR) Field Descriptions
Bits
Name
Value
Description
15-3
Reserved
Reserved
2
OST
Clear Flag for One-Shot Trip (OST) Latch
0
Has no effect. Always reads back a 0.
1
Clears this Trip (set) condition.
1
CBC
Clear Flag for Cycle-By-Cycle (CBC) Trip Latch
0
Has no effect. Always reads back a 0.
1
Clears this Trip (set) condition.
0
INT
Global Interrupt Clear Flag
0
Has no effect. Always reads back a 0.
1
Clears the trip-interrupt flag for this ePWM module (TZFLG[INT]).
NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If
the TZFLG[INT] bit is cleared and any of the other flag bits are set, then another interrupt
pulse will be generated. Clearing all flag bits will prevent further interrupts.
the TZFLG[INT] bit is cleared and any of the other flag bits are set, then another interrupt
pulse will be generated. Clearing all flag bits will prevent further interrupts.
Figure 4-22. Trip-Zone Force Register (TZFRC)
15
8
Reserved
R-0
7
3
2
1
0
Reserved
OST
CBC
Reserved
R-0
R/W-0
R/W-0
R- 0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-22. Trip-Zone Force Register (TZFRC) Field Descriptions
Bits
Name
Value
Description
15-3
Reserved
Reserved
2
OST
Force a One-Shot Trip Event via Software
0
Writing of 0 is ignored. Always reads back a 0.
1
Forces a one-shot trip event and sets the TZFLG[OST] bit.
1
CBC
Force a Cycle-by-Cycle Trip Event via Software
0
Writing of 0 is ignored. Always reads back a 0.
1
Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit.
0
Reserved
Reserved
through
and
through
describe the registers for the
event-trigger submodule.
110
Registers
SPRU791D – November 2004 – Revised October 2007