Motorola MC68HC908MR16 用户手册
Advance Information
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
180
Pulse-Width Modulator for Motor Control (PWMMC)
MOTOROLA
Pulse-Width Modulator for Motor Control
FPIN2 — State of Fault Pin 2 Bit
This read-only bit allows the user to read the current state of fault
pin 2.
pin 2.
1 = Fault pin 2 is at logic 1.
0 = Fault pin 2 is at logic 0.
0 = Fault pin 2 is at logic 0.
FFLAG2 — Fault Event Flag 2
The FFLAG2 event bit is set within two CPU cycles after a rising edge
on fault pin 2. To clear the FFLAG2 bit, the user must write a 1 to the
FTACK2 bit in the fault acknowledge register.
on fault pin 2. To clear the FFLAG2 bit, the user must write a 1 to the
FTACK2 bit in the fault acknowledge register.
1 = A fault has occurred on fault pin 2.
0 = No new fault on fault pin 2
0 = No new fault on fault pin 2
FPIN1 — State of Fault Pin 1 Bit
This read-only bit allows the user to read the current state of fault
pin 1.
pin 1.
1 = Fault pin 1 is at logic 1.
0 = Fault pin 1 is at logic 0.
0 = Fault pin 1 is at logic 0.
FFLAG1 — Fault Event Flag 1
The FFLAG1 event bit is set within two CPU cycles after a rising edge
on fault pin 1. To clear the FFLAG1 bit, the user must write a 1 to the
FTACK1 bit in the fault acknowledge register.
on fault pin 1. To clear the FFLAG1 bit, the user must write a 1 to the
FTACK1 bit in the fault acknowledge register.
1 = A fault has occurred on fault pin 1.
0 = No new fault on fault pin 1.
0 = No new fault on fault pin 1.
9.10.10 Fault Acknowledge Register
The fault acknowledge register (FTACK) is used to acknowledge and
clear the FFLAGs. In addition, it is used to monitor the current sensing
bits to test proper operation.
clear the FFLAGs. In addition, it is used to monitor the current sensing
bits to test proper operation.
Address: $0024
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
DT6
DT5
DT4
DT3
DT2
DT1
Write:
FTACK4
FTACK3
FTACK2
FTACK1
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-44. Fault Acknowledge Register (FTACK)