Samsung C8249 用户手册
16-BIT TIMER 0/1
S3C8245/P8245/C8249/P8249
12-4
Timer 0 Counter Register, High-Byte (T0CNTH)
F2H, Set 1, Bank 1, R
.7
.6
.5
.4
.3
.2
.1
.0
MSB
LSB
Reset Value: 00H
Timer 0 Counter Register, Low-Byte (T0CNTL)
F3H, Set 1, Bank 1, R
.7
.6
.5
.4
.3
.2
.1
.0
MSB
LSB
Reset Value: 00H
Figure 12-3. Timer 0 Counter Register (T0CNTH/L)
Timer 0 Data Register, High-Byte (T0DATAH)
F4H, Set 1, Bank 1, R/W
.7
.6
.5
.4
.3
.2
.1
.0
MSB
LSB
Reset Value: FFh
Timer 0 Data Register, Low-Byte (T0DATAL)
F5H, Set 1, Bank 1, R/W
.7
.6
.5
.4
.3
.2
.1
.0
MSB
LSB
Reset Value: FFh
Figure 12-4. Timer 0 Data Register (T0DATAH/L)