用户手册 — Freescale Semiconductor 56F8322

目录

• Part 1 Overview

  5
  • 1.1 56F8322/56F8122 Features

    5
    • 1.1.1 Hybrid Controller Core

      5
    • 1.1.2 Differences Between Devices

      5
    • 1.1.3 Memory

      6
    • 1.1.4 Peripheral Circuits

      6
    • 1.1.5 Energy Information

      7
  • 1.2 Device Description

    7
    • 1.2.1 56F8322 Features

      7
    • 1.2.2 56F8122 Features

      8
  • 1.3 Award-Winning Development Environment

    8
  • 1.4 Architecture Block Diagram

    9
  • 1.5 Product Documentation

    13
  • 1.6 Data Sheet Conventions

    13
• Part 2 Signal/Connection Descriptions

  14
  • 2.1 Introduction

    14
  • 2.2 Signal Pins

    17
• Part 3 On-Chip Clock Synthesis (OCCS)

  26
  • 3.1 Introduction

    26
  • 3.2 External Clock Operation

    26
    • 3.2.1 Crystal Oscillator

      26
    • 3.2.2 Ceramic Resonator (Default)

      27
    • 3.2.3 External Clock Source

      27
  • 3.3 Use of On-Chip Relaxation Oscillator

    28
  • 3.4 Internal Clock Operation

    28
  • 3.5 Registers

    29
• Part 4 Memory Map

  30
  • 4.1 Introduction

    30
  • 4.2 Program Map

    30
  • 4.3 Interrupt Vector Table

    31
  • 4.4 Data Map

    34
  • 4.5 Flash Memory Map

    34
  • 4.6 EOnCE Memory Map

    36
  • 4.7 Peripheral Memory Mapped Registers

    36
  • 4.8 Factory-Programmed Memory

    52
• Part 5 Interrupt Controller (ITCN)

  52
  • 5.1 Introduction

    52
  • 5.2 Features

    52
  • 5.3 Functional Description

    52
    • 5.3.1 Normal Interrupt Handling

      52
    • 5.3.2 Interrupt Nesting

      53
    • 5.3.3 Fast Interrupt Handling

      53
  • 5.4 Block Diagram

    54
  • 5.5 Operating Modes

    54
  • 5.6 Register Descriptions

    55
    • 5.6.1 Interrupt Priority Register 0 (IPR0)

      57
      • 5.6.1.1 Reserved—Bits 15–14

        57
      • 5.6.1.2 EOnCE Breakpoint Unit 0 Interrupt Priority Level (BKPT_U0 IPL)— Bits13–12

        57
      • 5.6.1.3 EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)— Bits 11–10

        57
      • 5.6.1.4 Reserved—Bits 9–0

        57
    • 5.6.2 Interrupt Priority Register 1 (IPR1)

      57
      • 5.6.2.1 Reserved—Bits 15–6

        58
      • 5.6.2.2 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)—Bits 5–4

        58
      • 5.6.2.3 EOnCE Transmit Register Empty Interrupt Priority Level (TX_REG IPL)—Bits 3–2

        58
      • 5.6.2.4 EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)— Bits 1–0

        58
    • 5.6.3 Interrupt Priority Register 2 (IPR2)

      58
      • 5.6.3.1 Flash Memory Command, Data, Address Buffers Empty Interrupt Priority Level (FMCBE IPL)—Bi...

        59
      • 5.6.3.2 Flash Memory Command Complete Priority Level (FMCC IPL)—Bits 13–12

        59
      • 5.6.3.3 Flash Memory Error Interrupt Priority Level (FMERR IPL)—Bits 11–10

        59
      • 5.6.3.4 PLL Loss of Lock Interrupt Priority Level (LOCK IPL)—Bits 9–8

        59
      • 5.6.3.5 Low Voltage Detector Interrupt Priority Level (LVI IPL)—Bits 7–6

        60
      • 5.6.3.6 Reserved—Bits 5–2

        60
      • 5.6.3.7 External IRQ A Interrupt Priority Level (IRQA IPL)—Bits 1–0

        60
    • 5.6.4 Interrupt Priority Register 3 (IPR3)

      60
      • 5.6.4.1 Reserved—Bits 15–10

        60
      • 5.6.4.2 FlexCAN Message Buffer Interrupt Priority Level (FCMSGBUF IPL)—Bits 9–8

        60
      • 5.6.4.3 FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)— Bits 7–6

        61
      • 5.6.4.4 FlexCAN Error Interrupt Priority Level (FCERR IPL)— Bits 5–4

        61
      • 5.6.4.5 FlexCAN Bus Off Interrupt Priority Level (FCBOFF IPL)— Bits 3–2

        61
      • 5.6.4.6 Reserved—Bits 1–0

        61
    • 5.6.5 Interrupt Priority Register 4 (IPR4)

      61
      • 5.6.5.1 SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)— Bits 15–14

        62
      • 5.6.5.2 SPI1 Transmit Empty Interrupt Priority Level (SPI1_XMIT IPL)— Bits 13–12

        62
      • 5.6.5.3 SPI1 Receiver Full Interrupt Priority Level (SPI1_RCV IPL)— Bits 11–10

        62
      • 5.6.5.4 Reserved—Bits 9–6

        62
      • 5.6.5.5 GPIO_A Interrupt Priority Level (GPIOA IPL)—Bits 5–4

        62
      • 5.6.5.6 GPIO_B Interrupt Priority Level (GPIOB IPL)—Bits 3–2

        63
      • 5.6.5.7 GPIO_C Interrupt Priority Level (GPIOC IPL)—Bits 1–0

        63
    • 5.6.6 Interrupt Priority Register 5 (IPR5)

      63
      • 5.6.6.1 Reserved—Bits 15–12

        63
      • 5.6.6.2 SCI1 Receiver Full Interrupt Priority Level (SCI1_RCV IPL)— Bits 11–10

        63
      • 5.6.6.3 SCI1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)— Bits 9–8

        64
      • 5.6.6.4 Reserved—Bits 7–6

        64
      • 5.6.6.5 SCI1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)— Bits 5–4

        64
      • 5.6.6.6 SCI1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)— Bits 3–2

        64
      • 5.6.6.7 SPI0 Transmitter Empty Interrupt Priority Level (SPI0_XMIT IPL)— Bits 1–0

        64
    • 5.6.7 Interrupt Priority Register 6 (IPR6)

      65
      • 5.6.7.1 Timer C, Channel 0 Interrupt Priority Level (TMRC_0 IPL)— Bits 15–14

        65
      • 5.6.7.2 Reserved—Bits 13–4

        65
      • 5.6.7.3 Quadrature Decoder 0, INDEX Pulse Interrupt Priority Level (DEC0_XIRQ IPL)—Bits 3–2

        65
      • 5.6.7.4 Quadrature Decoder 0, HOME Signal Transition or Watchdog Timer Interrupt Priority Level (...

        65
    • 5.6.8 Interrupt Priority Register 7 (IPR7)

      66
      • 5.6.8.1 Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL)— Bits 15–14

        66
      • 5.6.8.2 Reserved—Bits 13–6

        66
      • 5.6.8.3 Timer C, Channel 3 Interrupt Priority Level (TMRC3 IPL)—Bits 5–4

        66
      • 5.6.8.4 Timer C, Channel 2 Interrupt Priority Level (TMRC2 IPL)—Bits 3–2

        66
      • 5.6.8.5 Timer C, Channel 1 Interrupt Priority Level (TMRC1 IPL)—Bits 1–0

        67
    • 5.6.9 Interrupt Priority Register 8 (IPR8)

      67
      • 5.6.9.1 SCI0 Receiver Full Interrupt Priority Level (SCI0_RCV IPL)— Bits 15–14

        67
      • 5.6.9.2 SCI0 Receiver Error Interrupt Priority Level (SCI0_RERR IPL)— Bits 13–12

        67
      • 5.6.9.3 Reserved—Bits 11–10

        67
      • 5.6.9.4 SCI0 Transmitter Idle Interrupt Priority Level (SCI0_TIDL IPL)— Bits 9–8

        68
      • 5.6.9.5 SCI0 Transmitter Empty Interrupt Priority Level (SCI0_XMIT IPL)— Bits 7–6

        68
      • 5.6.9.6 Timer A, Channel 3 Interrupt Priority Level (TMRA3 IPL)—Bits 5–4

        68
      • 5.6.9.7 Timer A, Channel 2 Interrupt Priority Level (TMRA2 IPL)—Bits 3–2

        68
      • 5.6.9.8 Timer A, Channel 1 Interrupt Priority Level (TMRA1 IPL)—Bits 1–0

        69
    • 5.6.10 Interrupt Priority Register 9 (IPR9)

      69
      • 5.6.10.1 PWM A Fault Interrupt Priority Level (PWMAF IPL)—Bits 15–14

        69
      • 5.6.10.2 Reserved—Bits 13–12

        69
      • 5.6.10.3 Reload PWM A Interrupt Priority Level (PWMA_RL IPL)— Bits 11–10

        69
      • 5.6.10.4 Reserved—Bits 9–8

        69
      • 5.6.10.5 ADC A Zero Crossing or Limit Error Interrupt Priority Level (ADCA_ZC IPL)—Bits 7–6

        70
      • 5.6.10.6 Reserved—Bits 5–4

        70
      • 5.6.10.7 ADC A Conversion Complete Interrupt Priority Level (ADCA_CC IPL)—Bits 3–2

        70
      • 5.6.10.8 Reserved—Bits 1–0

        70
    • 5.6.11 Vector Base Address Register (VBA)

      70
      • 5.6.11.1 Reserved—Bits 15–13

        70
      • 5.6.11.2 Interrupt Vector Base Address (VECTOR BASE ADDRESS)— Bits 12–0

        70
    • 5.6.12 Fast Interrupt 0 Match Register (FIM0)

      71
      • 5.6.12.1 Reserved—Bits 15–7

        71
      • 5.6.12.2 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 6–0

        71
    • 5.6.13 Fast Interrupt 0 Vector Address Low Register (FIVAL0)

      71
      • 5.6.13.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0

        71
    • 5.6.14 Fast Interrupt 0 Vector Address High Register (FIVAH0)

      71
      • 5.6.14.1 Reserved—Bits 15–5

        71
      • 5.6.14.2 Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0

        72
    • 5.6.15 Fast Interrupt 1 Match Register (FIM1)

      72
      • 5.6.15.1 Reserved—Bits 15–7

        72
      • 5.6.15.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 6–0

        72
    • 5.6.16 Fast Interrupt 1 Vector Address Low Register (FIVAL1)

      72
      • 5.6.16.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0

        72
    • 5.6.17 Fast Interrupt 1 Vector Address High Register (FIVAH1)

      72
      • 5.6.17.1 Reserved—Bits 15–5

        73
      • 5.6.17.2 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0

        73
    • 5.6.18 IRQ Pending 0 Register (IRQP0)

      73
      • 5.6.18.1 IRQ Pending (PENDING)—Bits 16–2

        73
      • 5.6.18.2 Reserved—Bit 0

        73
    • 5.6.19 IRQ Pending 1 Register (IRQP1)

      73
      • 5.6.19.1 IRQ Pending (PENDING)—Bits 32–17

        73
    • 5.6.20 IRQ Pending 2 Register (IRQP2)

      74
      • 5.6.20.1 IRQ Pending (PENDING)—Bits 48–33

        74
    • 5.6.21 IRQ Pending 3 Register (IRQP3)

      74
      • 5.6.21.1 IRQ Pending (PENDING)—Bits 64–49

        74
    • 5.6.22 IRQ Pending 4 Register (IRQP4)

      74
      • 5.6.22.1 IRQ Pending (PENDING)—Bits 80–65

        74
    • 5.6.23 IRQ Pending 5 Register (IRQP5)

      75
      • 5.6.23.1 Reserved—Bits 96–82

        75
      • 5.6.23.2 IRQ Pending (PENDING)—Bit 81

        75
    • 5.6.24 Reserved—Base + 17

      75
    • 5.6.25 Reserved—Base + 18

      75
    • 5.6.26 Reserved—Base + 19

      75
    • 5.6.27 Reserved—Base + 1A

      75
    • 5.6.28 Reserved—Base + 1B

      75
    • 5.6.29 Reserved—Base + 1C

      75
    • 5.6.30 ITCN Control Register (ICTL)

      75
      • 5.6.30.1 Interrupt (INT)—Bit 15

        75
      • 5.6.30.2 Interrupt Priority Level (IPIC)—Bits 14–13

        76
      • 5.6.30.3 Vector Number - Vector Address Bus (VAB)—Bits 12–6

        76
      • 5.6.30.4 Interrupt Disable (INT_DIS)—Bit 5

        76
      • 5.6.30.5 Reserved—Bit 4

        76
      • 5.6.30.6 Reserved—Bit 3

        76
      • 5.6.30.7 IRQA State Pin (IRQA STATE)—Bit 2

        76
      • 5.6.30.8 Reserved—Bit 1

        76
      • 5.6.30.9 IRQA Edge Pin (IRQA Edg)—Bit 0

        76
  • 5.7 Resets

    77
    • 5.7.1 Reset Handshake Timing

      77
    • 5.7.2 ITCN After Reset

      77
• Part 6 System Integration Module (SIM)

  77
  • 6.1 Introduction

    77
  • 6.2 Features

    78
  • 6.3 Operating Modes

    78
  • 6.4 Operating Mode Register

    79
  • 6.5 Register Descriptions

    79
    • 6.5.1 SIM Control Register (SIM_CONTROL)

      80
      • 6.5.1.1 Reserved—Bits 15–6

        80
      • 6.5.1.2 OnCE Enable (ONCE EBL)—Bit 5

        81
      • 6.5.1.3 Software Reset (SW RST)—Bit 4

        81
      • 6.5.1.4 Stop Disable (STOP_DISABLE)—Bits 3–2

        81
      • 6.5.1.5 Wait Disable (WAIT_DISABLE)—Bits 1–0

        81
    • 6.5.2 SIM Reset Status Register (SIM_RSTSTS)

      81
      • 6.5.2.1 Reserved—Bits 15–6

        81
      • 6.5.2.2 Software Reset (SWR)—Bit 5

        81
      • 6.5.2.3 COP Reset (COPR)—Bit 4

        82
      • 6.5.2.4 External Reset (EXTR)—Bit 3

        82
      • 6.5.2.5 Power-On Reset (POR)—Bit 2

        82
      • 6.5.2.6 Reserved—Bits 1–0

        82
    • 6.5.3 SIM Software Control Registers (SIM_SCR0, SIM_SCR1, SIM_SCR2, and SIM_SCR3)

      82
      • 6.5.3.1 Software Control Data 1 (FIELD)—Bits 15–0

        82
    • 6.5.4 Most Significant Half of JTAG ID (SIM_MSH_ID)

      83
    • 6.5.5 Least Significant Half of JTAG ID (SIM_LSH_ID)

      83
    • 6.5.6 SIM Pull-up Disable Register (SIM_PUDR)

      83
      • 6.5.6.1 Reserved—Bits 15–12

        83
      • 6.5.6.2 RESET—Bit 11

        83
      • 6.5.6.3 IRQ—Bit 10

        84
      • 6.5.6.4 Reserved—Bits 9–4

        84
      • 6.5.6.5 JTAG—Bit 3

        84
      • 6.5.6.6 Reserved—Bits 2–0

        84
    • 6.5.7 CLKO Select Register (SIM_CLKOSR)

      84
      • 6.5.7.1 Reserved—Bits 15–10

        84
      • 6.5.7.2 PHASEA0 (PHSA)—Bit 9

        84
      • 6.5.7.3 PHASEB0 (PHSB)—Bit 8

        84
      • 6.5.7.4 INDEX0 (INDEX)—Bit 7

        85
      • 6.5.7.5 HOME0 (HOME)—Bit 6

        85
      • 6.5.7.6 Clockout Disable (CLKDIS)—Bit 5

        85
      • 6.5.7.7 CLockout Select (CLKOSEL)—Bits 4–0

        85
    • 6.5.8 SIM GPIO Peripheral Select Register (SIM_GPS)

      85
      • 6.5.8.1 Reserved—Bits 15–8

        86
      • 6.5.8.2 GPIO C6 (C6)—Bit 7

        86
      • 6.5.8.3 GPIOC5 (C5)—Bit 6

        86
      • 6.5.8.4 GPIOB1 (B1)—Bit 5

        87
      • 6.5.8.5 GPIOB0 (B0)—Bit 4

        87
      • 6.5.8.6 GPIOA5 (A5)—Bit 3

        87
      • 6.5.8.7 GPIOA4 (A4)—Bit 2

        87
      • 6.5.8.8 GPIOA3 (A3)—Bit 1

        87
      • 6.5.8.9 GPIOA2 (A2)—Bit 0

        87
    • 6.5.9 Peripheral Clock Enable Register (SIM_PCE)

      87
      • 6.5.9.1 Reserved—Bits 15–14

        88
      • 6.5.9.2 Analog-to-Digital Converter A Enable (ADCA)—Bit 13

        88
      • 6.5.9.3 FlexCAN Enable (CAN)—Bit 12

        88
      • 6.5.9.4 Reserved—Bit 11

        88
      • 6.5.9.5 Decoder 0 Enable (DEC0)—Bit 10

        88
      • 6.5.9.6 Reserved—Bit 9

        88
      • 6.5.9.7 Quad Timer C Enable (TMRC)—Bit 8

        88
      • 6.5.9.8 Reserved—Bit 7

        88
      • 6.5.9.9 Quad Timer A Enable (TMRA)—Bit 6

        88
      • 6.5.9.10 Serial Communications Interface 1 Enable (SCI1)—Bit 5

        89
      • 6.5.9.11 Serial Communications Interface 0 Enable (SCI0)—Bit 4

        89
      • 6.5.9.12 Serial Peripheral Interface 1 Enable (SPI1)—Bit 3

        89
      • 6.5.9.13 Serial Peripheral Interface 0 Enable (SPI0)—Bit 2

        89
      • 6.5.9.14 Reserved—Bit 1

        89
      • 6.5.9.15 Pulse Width Modulator A Enable (PWMA)—Bit 0

        89
    • 6.5.10 I/O Short Address Location Register (SIM_ISALH and SIM_ISALL)

      89
      • 6.5.10.1 Input/Output Short Address Low (ISAL[23:22])—Bit 1–0

        90
      • 6.5.10.2 Input/Output Short Address Low (ISAL[21:6])—Bit 15–0

        91
  • 6.6 Clock Generation Overview

    91
  • 6.7 Power-Down Modes

    91
  • 6.8 Stop and Wait Mode Disable Function

    92
  • 6.9 Resets

    92
• Part 7 Security Features

  93
  • 7.1 Operation with Security Enabled

    93
  • 7.2 Flash Access Blocking Mechanisms

    93
    • 7.2.1 Forced Operating Mode Selection

      93
    • 7.2.2 Disabling EOnCE Access

      93
    • 7.2.3 Flash Lockout Recovery

      94
    • 7.2.4 Product Analysis

      95
• Part 8 General Purpose Input/Output (GPIO)

  96
  • 8.1 Introduction

    96
  • 8.2 Configuration

    96
  • 8.3 Memory Maps

    98
• Part 9 Joint Test Action Group (JTAG)

  98
  • 9.1 JTAG Information

    98
• Part 10 Specifications

  99
  • 10.1 General Characteristics

    99
  • 10.2 DC Electrical Characteristics

    103
    • 10.2.1 Voltage Regulator Specifications

      105
    • 10.2.2 Temperature Sense

      107
  • 10.3 AC Electrical Characteristics

    107
  • 10.4 Flash Memory Characteristics

    108
  • 10.5 External Clock Operation Timing

    109
  • 10.6 Phase Locked Loop Timing

    110
  • 10.7 Oscillator Parameters

    110
  • 10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing

    113
  • 10.9 Serial Peripheral Interface (SPI) Timing

    115
  • 10.10 Quad Timer Timing

    118
  • 10.11 Quadrature Decoder Timing

    118
  • 10.12 Serial Communication Interface (SCI) Timing

    119
  • 10.13 Controller Area Network (CAN) Timing

    120
  • 10.14 JTAG Timing

    120
  • 10.15 Analog-to-Digital Converter (ADC) Parameters

    122
  • 10.16 Equivalent Circuit for ADC Inputs

    125
  • 10.17 Power Consumption

    125
• Part 11 Packaging

  127
  • 11.1 56F8322 Package and Pin-Out Information

    127
  • 11.2 56F8122 Package and Pin-Out Information

    129
• Part 12 Design Considerations

  132
  • 12.1 Thermal Design Considerations

    132
  • 12.2 Electrical Design Considerations

    133
  • 12.3 Power Distribution and I/O Ring Implementation

    134
• Part 13 Ordering Information

  135