用户手册 — Fujitsu FR60

目录

• CONTROLLER MANUAL

  1
• FR60

  1
  • 32-BIT MICROCONTROLLER

    1
• MB91460 Series

  1
  • User’s Manual

    1
  • Version 1.00

    1
  • - PRELIMINARY -

    1
• FR60

  3
  • 32-BIT MICROCONTROLLER

    3
• MB91460 Series

  3
  • User’s Manual

    3
• Chapter 1 Introduction

  17
  • 1. How to Handle the Device

    17
    • To set latch-up prevention

      17
    • Termination of unused pin

      17
    • Power-supply pin

      17
    • Crystal-oscillator circuit

      17
    • NC and OPEN pin termination

      17
    • Mode pins (from MD0 to MD2)

      17
    • At the time of power-on

      17
    • Source oscillation input at the time of power-on

      17
    • Caution: during the PLL clock operation

      18
    • For more specification about operating voltage, see the latest data sheet.

      18
  • 2. Instruction for Users

    19
  • 3. Caution: debug-related matters

    22
  • 4. How to Use This Document

    23
• Chapter 2 MB91460 Rev.A/Rev.B Overview

  27
  • 1. Overview

    27
  • 2. Features

    27
    • 2.1 FR60 CPU Core

      27
    • 2.2 Instruction Cache

      27
    • 2.3 Interrupt Controller

      28
    • 2.4 Internal Data RAM

      28
    • 2.5 Internal Instruction/Data RAM

      28
    • 2.6 Embedded Instruction/Data Memory

      28
    • 2.7 External Bus Interface

      28
    • 2.8 DMA Controller

      28
    • 2.9 Infotainment extension (MB91460 Rev.B)

      29
    • 2.10 Peripheral Function

      30
  • 3. MB91460 Series Product Lineup

    35
  • 4. Block Diagram

    37
• Chapter 3 MB91460 Series Basic Information

  39
  • 1. Memory Map

    39
  • 2. I/O Map

    40
  • 3. Interrupt Vector Table

    89
  • 4. Package

    94
  • 5. Pin Assignment Diagram

    95
  • 6. Pin Definitions

    96
  • 7. I/O Circuit Type

    110
  • 8. Pin State Table

    112
• Chapter 4 CPU Architecture

  121
  • 1. Overview

    121
  • 2. Features

    122
  • 3. CPU

    123
  • 4. 32-bit/16-bit Bus Converter

    123
  • 5. Harvard/Princeton Bus Converter

    123
  • 6. Instruction Overview

    124
  • 7. Data Structure

    125
  • 8. Word Alignment

    126
  • 9. Addressing

    127
• Chapter 5 CPU Registers

  129
  • 1. General-purpose Registers

    129
  • 2. Dedicated Registers

    129
    • 2.1 PC: Program Counter

      130
    • 2.2 PS: Program Status Register

      130
    • 2.3 TBR: Table-base Register

      134
    • 2.4 RP: Return Pointer

      134
    • 2.5 SSP: System Stack Pointer

      134
    • 2.6 USP: User Stack Pointer

      135
    • 2.7 MDH, MDL: Multiply & Divide Register

      136
• Chapter 6 EIT: Exceptions, Interrupts and Traps

  137
  • 1. Overview

    137
  • 2. Features

    137
  • 3. EIT Trigger

    137
  • 4. Return from EIT

    137
  • 5. EIT Interrupt Level

    138
  • 6. EIT Vector Table

    138
  • 7. Multiple EIT Processing

    139
  • 8. Operation

    141
    • 8.1 User Interrupt operation

      141
    • 8.2 Operation of INT Instruction

      142
    • 8.3 Operation of INTE Instruction

      142
    • 8.4 Operation of Step Trace Trap

      143
    • 8.5 Operation of Undefined-instruction Exception

      143
    • 8.6 Coprocessor Absent Trap

      144
    • 8.7 Coprocessor Error Trap

      144
    • 8.8 Operation of RETI Instruction

      144
  • 9. Caution

    144
• Chapter 7 Branch Instruction

  145
  • 1. Branch Instruction with Delay Slot

    145
  • 2. Operation of Branch Instruction with Delay Slot

    145
  • 3. Actual Example (with Delay Slot)

    146
    • 3.1 JMP:D @Ri / CALL:D @Ri Instruction

      146
    • 3.2 RET:D Instruction

      146
    • 3.3 Bcc:D rel Instruction

      146
    • 3.4 CALL:D Instruction

      146
  • 4. Restrictions on Branch Instruction with Delay Slot

    147
    • 4.1 Available Instructions for Delay Slot

      147
    • 4.2 Step Trace Trap

      147
    • 4.3 Interrupt

      147
    • 4.4 Undefined-instruction Exception

      147
  • 5. Branch Instruction without Delay Slot

    148
  • 6. Operation of Branch Instruction without Delay Slot

    148
• Chapter 8 Device State Transition

  149
  • 1. Overview

    149
  • 2. Features

    149
  • 3. State Transition Diagram

    150
    • 3.1 RUN (Normal Operation)

      151
    • 3.2 SLEEP

      151
    • 3.3 STOP

      151
    • 3.4 Oscillation-stabilization-wait RUN

      151
    • 3.5 Oscillation-stabilization-wait Reset

      152
    • 3.6 Operation-initialization Reset (RST)

      152
    • 3.7 Setting-initialization Reset (INIT)

      152
    • 3.8 Priority of Each Request of State Transition

      152
• Chapter 9 Reset

  155
  • 1. Overview

    155
  • 2. Features

    155
  • 3. Configuration

    156
  • 4. Registers

    157
    • 4.1 RSRR: Reset Cause Register

      157
    • 4.2 STCR: Standby Control Register

      159
    • 4.3 MOD: Mode Pins

      160
    • 4.4 Mode Vector

      160
    • 4.5 Reset Vector

      160
    • 4.6 Device Mode Overview

      161
  • 5. INIT Pin Input (INIT: Settings Initialization Reset)

    162
    • 5.1 Trigger

      162
    • 5.2 Releasing the Reset Request

      162
    • 5.3 Flag

      162
    • 5.4 Reset Level

      162
    • 5.5 Initialization Triggered by INIT Pin Input (INIT)

      162
    • 5.6 Reset Cancellation Sequence

      163
  • 6. Watchdog Reset (INIT: Settings Initialization Reset)

    164
    • 6.1 Trigger

      164
    • 6.2 Releasing the Reset Request

      164
    • 6.3 Flag

      164
    • 6.4 Reset Level

      164
    • 6.5 Initialization Triggered by Watchdog Reset (INIT)

      164
    • 6.6 Reset Cancellation Sequence

      164
  • 7. Software Reset (RST: Operation Initialization Reset)

    165
    • 7.1 Trigger

      165
    • 7.2 Releasing the Reset Request

      165
    • 7.3 Flag

      165
    • 7.4 Reset Level

      165
    • 7.5 Items Initialized by Operation Reset (RST)

      165
    • 7.6 Reset Cancellation Sequence

      165
  • 8. Reset Operation Modes

    166
    • 8.1 Normal (Asynchronous) Reset Mode

      166
    • 8.2 Synchronous Reset Operation

      166
  • 9. MCU Operation Mode

    167
    • 9.1 Bus Modes and Access Modes

      167
      • Single chip mode

        167
      • Internal ROM, external bus mode

        167
      • External ROM, external bus mode

        167
  • 10. Caution

    168
• Chapter 10 Standby

  171
  • 1. Overview

    171
  • 2. Features

    171
  • 3. Configuration

    172
  • 4. Registers

    173
    • 4.1 STCR: Standby Control Register

      173
    • 4.2 TBCR: Timebase timer control register

      174
  • 5. Operation

    175
    • 5.1 Sleep Mode

      175
    • 5.2 Stop mode

      176
  • 6. Settings

    177
  • 7. Q&A

    177
    • 7.1 How do I change to sleep mode?

      177
    • 7.2 How do I change to stop mode?

      178
    • 7.3 How do I set pins to high impedance (Hi-z) during stop mode?

      178
    • 7.4 How do I halt the main clock oscillation during stop mode?

      178
    • 7.5 How do I recover from sleep mode?

      178
    • 7.6 How do I recover from stop mode?

      179
  • 8. Caution

    181
• Chapter 11 Memory Controller

  183
  • 1. Overview

    183
  • 2. FLASH Interface

    183
  • 3. General Purpose RAM

    183
  • 4. Instruction Cache and Data Buffer

    183
  • 5. Prefetch

    183
  • 6. Fixed Mode and Reset Vectors

    183
  • 7. Registers

    184
    • List of FLASH-IF Registers

      184
  • 8. Explanations of Registers

    185
    • FLASH Interface Control Register

      185
    • FLASH Memory Wait Timing Register (FMWT)

      191
    • FLASH Memory Adddress Check register (FMAC)

      194
    • Non-cacheable area definition

      194
• Chapter 12 Instruction Cache

  195
  • 1. General description

    195
  • 2. Main body structure

    195
    • Control register structure

      197
  • 3. Operating mode conditions

    201
    • Cache status in various operating modes

      201
    • Cache Entry Update

      202
  • 4. Cacheable areas in the instruction cache

    202
  • 5. Settings for handling the I-Cache

    202
• Chapter 13 Clock Control

  205
  • 1. Overview

    205
  • 2. Features

    205
  • 3. Configuration

    206
  • 4. Registers

    207
    • 4.1 CLKR: Clock Source Control Register

      207
    • 4.2 DIV0R: Clock Division Setting Register 0

      209
    • 4.3 DIV1R: Clock Division Setting Register 1

      211
    • 4.4 CSCFG: Clock Source Configuration Register

      212
    • 4.5 OSCCR: Oscillation Control Register

      214
  • 5. Operation

    215
    • 5.1 Clock Setup Sequence (Example)

      215
    • 5.2 Halting and Restarting the Main Clock Oscillation During Subclock Mode (Example)

      215
    • 5.3 Notes

      216
  • 6. Settings

    217
  • 7. Q & A

    218
    • 7.1 How do I enable or disable clock operation?

      218
    • 7.2 How do I select the main PLL multiplier ratio?

      218
    • 7.3 How do I select the operating clock source?

      218
    • 7.4 How do I set the operation clock division ratios?

      219
    • 7.5 How do I halt the main clock in sub clock mode?

      220
    • 7.6 How do I halt the sub clock in sub clock on RC oscillator mode?

      220
    • 7.7 How do I halt the sub clock in main clock mode?

      220
  • 8. Caution

    221
• Chapter 14 PLL Interface

  223
  • 1. Overview

    223
  • 2. Features

    223
  • 3. Frequency calculation

    223
  • 4. Registers

    224
    • 4.1 PLL Control Registers

      224
  • 5. Recommended Settings

    228
  • 6. Clock Auto Gear Up/Down

    229
  • 7. Caution

    231
• Chapter 15 CAN Clock Prescaler

  233
  • 1. Overview

    233
  • 2. Features

    233
  • 3. Registers

    234
    • 3.1 CAN Clock Control Register

      234
• Chapter 16 Clock Supervisor

  237
  • 1. Overview Clock Supervisor

    237
  • 2. Clock Supervisor Register

    238
  • 3. Block Diagram Clock Supervisor

    240
  • 4. Operation Modes

    241
• Chapter 17 Clock Modulator

  255
  • 1. Overview

    255
    • Modulation degree and frequency resolution in frequency modulation mode

      255
  • 2. Clock Modulator Registers

    256
    • Clock modulator registers

      256
    • Clock Modulator Control Register (CMCR)

      257
    • Clock modulator control register contents

      258
    • Clock Modulation Parameter Register (CMPR)

      260
    • Modulation parameter register contents

      260
  • 3. Application Note

    263
    • Recommended startup sequence for frequency modulation mode

      263
    • Modulation parameter for frequency modulation mode

      263
    • Recommended settings

      264
• Chapter 18 Timebase Counter

  265
  • 1. Overview

    265
  • 2. Features

    265
    • 2.1 Timebase Counter (when used to generate the oscillation stabilization wait)

      265
    • 2.2 Events that Invoke an Oscillation Stabilization Wait

      265
      • Wait time after a settings initialization: Invoked automatically (timebase counter)

        265
      • Wait time after recovering from stop mode: Invoked automatically (timebase counter)

        265
      • When recovering from abnormal state with main PLL selected

        265
      • Wait time after power on: Provided by pin input

        266
      • Wait time after changing from subclock to main clock: Using the main oscillation stabilization wait timer to generate this time is recommended.

        266
      • When recovering from main clock oscillation halted: Enabling the main clock oscillation and waiting for oscillation to stabilize is required.

        266
      • Main PLL lock wait time (for main clock operation): Using the timebase timer interrupt to generate this time is recommended.

        266
  • 3. Configuration

    266
  • 4. Registers

    267
    • 4.1 STCR: Standby Control Register

      267
    • 4.2 CLKR: Clock Source Control Register

      268
  • 5. Operation

    269
    • 5.1 INIT Pin Input

      269
    • 5.2 Watchdog Reset (The specified oscillation stabilization wait time is generated automatically)

      270
    • 5.3 Recovering from Stop Mode via an Interrupt

      271
    • 5.4 The lock wait time for the main PLL must be generated by software.

      272
    • 5.5 Generating an Oscillation Stabilization Wait when Changing from Subclock Mode to Main Clock Mode

      272
    • 5.6 When Recovering from an Abnormal State with the Main PLL Selected

      272
    • 5.7 Types of Oscillation Stabilization Wait

      273
    • 5.8 Whether or not a Stabilization Wait is Required for Each State Transition

      274
  • 6. Settings

    275
  • 7. Q&A

    276
    • 7.1 How do I setup the oscillation stabilization wait time that is generated automatically?

      276
    • 7.2 How do I set the oscillation stabilization wait time without generating it automatically?

      277
    • 7.3 What is the clear timing for the timebase counter?

      277
  • 8. Caution

    278
• Chapter 19 Timebase Timer

  279
  • 1. Overview

    279
  • 2. Features

    279
  • 3. Configuration

    280
  • 4. Register

    281
    • 4.1 TBCR: Timebase Timer Control Register

      281
    • 4.2 CTBR: Timebase Counter Clear Register

      282
  • 5. Operation

    283
    • 5.1 Timebase Timer Interrupt Example (Main PLL Lock Wait)

      283
  • 6. Setting

    284
  • 7. Q & A

    285
    • 7.1 What are the types of interval time used in the timebase timer (and the timebase counter used by the timebase timer) and how to select them?

      285
    • 7.2 What Is the count clock of the timebase counter?

      285
    • 7.3 How to operate the timebase timer?

      285
    • 7.4 How is the timebase timer (=timebase counter) operation stopped?

      285
    • 7.5 How is the timebase counter (=timebase timer) cleared?

      285
    • 7.6 How about the interrupt-associated registers?

      285
    • 7.7 What are the interrupt types?

      286
    • 7.8 How is an interrupt enabled?

      286
  • 8. Caution

    287
• Chapter 20 Software Watchdog Timer

  289
  • 1. Overview

    289
  • 2. Features

    289
  • 3. Configuration

    290
  • 4. Register

    291
    • 4.1 RSRR: Watchdog Timer Control Register

      291
    • 4.2 WPR: Watchdog Reset Generation Postponement Register

      293
    • 4.3 CTBR: Timebase Counter Clear Register

      293
  • 5. Operation

    294
    • 5.1 Watchdog (Detecting Runaway)

      294
    • 5.2 Starting the Watchdog Timer and Setting the Watchdog Timer Period

      295
    • 5.3 Postponing the Generation of a Watchdog Reset

      295
    • 5.4 Confirming that the Watchdog Reset has been Generated

      295
    • 5.5 Temporarily Stopped Watchdog Timer (Automatic Generation Postponement)

      295
    • 5.6 Stopping the Watchdog Timer

      295
  • 6. Setting

    296
  • 7. Q & A

    297
    • 7.1 What are the types of watchdog interval time and how are they selected?

      297
    • 7.2 How is the watchdog operation started (set to valid)?

      297
    • 7.3 How can we check that the watchdog reset has been generated?

      297
    • 7.4 How is the watchdog stopped?

      297
    • 7.5 How do I clear the watchdog timer (1-bit counter)?

      297
  • 8. Caution

    298
• Chapter 21 Hardware Watchdog Timer

  299
  • 1. Overview

    299
    • Hardware watchdog timer

      299
  • 2. Configuration

    300
    • Block diagram of the hardware watchdog timer

      300
  • 3. Register

    301
    • 3.1 Hardware watchdog timer control and status register

      301
    • 3.2 Hardware watchdog timer duration register

      302
  • 4. Functions

    303
    • Function of the hardware watchdog timer

      303
    • Period of the hardware watchdog timer

      303
  • 5. Caution

    304
    • Software disabling is not possible

      304
    • Hardware disabling is only possible on the evaluation device MB91V460

      304
    • Postponement of reset

      304
    • Timer stop and clear

      304
    • During DMA transfer

      304
    • Duration setting

      304
    • RC clock frequency

      304
• Chapter 22 Main Oscillation Stabilisation Timer

  305
  • 1. Overview

    305
  • 2. Features

    305
  • 3. Configuration

    306
  • 4. Register

    307
    • 4.1 OSCRH: Control Register for the Main Clock Oscillation Stability Wait Timer

      307
  • 5. Operation

    308
    • 5.1 Main Clock Oscillation Stability Wait

      308
    • 5.2 Interval Interrupt

      309
  • 6. Setting

    310
  • 7. Q & A

    311
    • 7.1 What are the types of interval time (wait time) and how are they selected?

      311
    • 7.2 How do I select the count clock?

      311
    • 7.3 How is the main clock oscillation stability wait timer count operation enabled/ disabled?

      311
    • 7.4 How is the main clock oscillation stability wait timer cleared?

      311
    • 7.5 What happens with the interrupt-associated registers?

      311
    • 7.6 What are the types of interrupt?

      312
    • 7.7 how is an interrupt enabled?

      312
    • 7.8 How is the main clock oscillation stability wait timer stopped counting?

      312
  • 8. Caution

    313
• Chapter 23 Sub Oscillation Stabilisation Timer

  315
  • 1. Overview

    315
  • 2. Features

    315
  • 3. Configuration

    316
  • 4. Register

    317
    • 4.1 WPCRH: Sub oscillation stabilisation timer Control Register

      317
  • 5. Operation

    319
    • 5.1 Subclock Oscillation Stability Wait Interrupt

      319
    • 5.2 Interval Interrupt (Clock Interrupt)

      320
    • 5.3 Returning from the Stop Mode due to Interval Operation (Clock Interrupt)

      321
  • 6. Setting

    322
  • 7. Q & A

    323
    • 7.1 What are the types of interval time (wait time) and how are they selected?

      323
    • 7.2 How is the count clock selected?

      323
    • 7.3 How is the sub oscillation stabilisation timer cleared?

      323
    • 7.4 What are interrupt-associated registers?

      323
    • 7.5 What are the types of interrupt?

      323
    • 7.6 How is the interrupt enabled?

      324
    • 7.7 How is the sub oscillation stabilisation timer stopped counting?

      324
  • 8. Caution

    325
• Chapter 24 Interrupt Control

  327
  • 1. Overview

    327
  • 2. Features

    327
  • 3. Configuration

    328
  • 4. Registers

    329
    • 4.1 ICR: Interrupt Control Register

      329
    • 4.2 Interrupt Vector

      333
  • 5. Operation

    334
  • 6. Setting

    335
  • 7. Q & A

    335
    • 7.1 How can I set interrupt levels?

      335
    • 7.2 How do I enable interrupts?

      335
    • 7.3 How do I disable interrupts?

      335
    • 7.4 How can I set an I flag?

      336
  • 8. Caution

    336
• Chapter 25 External Interrupt

  337
  • 1. Overview

    337
  • 2. Features

    337
  • 3. Configuration

    338
  • 4. Registers

    341
    • 4.1 ELVR: Interrupt Request Level Register

      341
    • 4.2 EIRR: Interrupt Request Register

      342
    • 4.3 ENIR: Interrupt Request Enable Register

      342
  • 5. Operation

    343
  • 6. Setting

    344
  • 7. Q & A

    344
    • 7.1 What are the types and setting procedures of detect levels?

      344
    • 7.2 How do I set INT pin as the input?

      344
    • 7.3 What interrupt registers are used?

      345
    • 7.4 Interrupt types

      345
    • 7.5 How do I enable, disable, and clear interrupts?

      346
  • 8. Caution

    347
• Chapter 26 DMA Controller

  349
  • 1. Overview of the DMA Controller (DMAC)

    349
    • Priority (ch.0>ch.1>ch.2>ch.3>ch.4)

      349
    • The order can be rotated between ch.0 and ch.1.

      349
    • DMAC start sources

      349
    • Transfer mode

      349
  • 2. DMA Controller (DMAC) Registers

    351
    • 2.1 Control/Status Registers A (DMACA0 to 4)

      352
    • 2.2 Control/Status Registers B (DMACB0 to 4)

      359
    • 2.3 Transfer Source/Transfer Destination Address Setting Registers (DMASA0 to 4/ DMADA0 to 4)

      366
    • 2.4 DMAC All-Channel Control Register (DMACR)

      367
    • 2.5 Other Functions

      368
  • 3. DMA Controller (DMAC) Operation

    370
    • Block/step transfer

      370
    • Burst transfer

      370
    • Demand transfer

      370
    • 2-cycle transfer (normal transfer)

      370
    • Fly-by transfer (memory --> I/O)

      370
    • Fly-by transfer (I/O --> memory)

      371
    • Specifying the address for a 2-cycle transfer

      371
    • Specifying the address for a fly-by transfer

      371
    • Transfer count

      371
    • Transfer end

      371
    • 3.1 Setting a Transfer Request

      372
      • Edge detection

        372
      • Level detection

        372
    • 3.2 Transfer Sequence

      373
      • Burst 2-cycle transfer

        373
      • Burst fly-by transfer

        374
      • Demand Transfer 2-Cycle Transfer

        374
      • Demand transfer fly-by transfer

        375
      • Step/block transfer 2-cycle transfer

        375
      • Step/block transfer fly-by transfer

        376
    • 3.3 General Aspects of DMA Transfer

      376
      • Transfer count register reloading

        377
      • Transfer source address register reloading

        377
      • Transfer destination address register reloading

        377
      • Special examples of operating mode and the reload operation

        377
    • 3.4 Addressing Mode

      377
    • 3.5 Data Types

      378
    • 3.6 Transfer Count Control

      378
    • 3.7 CPU Control

      379
    • 3.8 Hold Arbitration

      380
    • 3.9 Operation from Starting to End/Stopping

      380
      • Enabling operation for all channels

        380
      • Starting transfer

        380
      • Starting from a temporary stop

        380
      • Setting of temporary stopping by writing to the control register (Set independently for each channel or all channels simultaneously)

        381
      • NMI/hold suppress level interrupt processing

        381
      • Transfer end

        381
      • Disabling all channels

        382
      • Transfer stop requests from peripheral circuits

        382
    • 3.10 DMAC Interrupt Control

      383
    • 3.11 Channel Selection and Control

      384
      • Fixed mode

        384
      • Rotation mode (ch.0 to ch.1 only)

        384
    • 3.12 Supplement on External Pin and Internal Operation Timing

      385
      • For 2-cycle transfer

        385
      • For fly-by (read/write) transfer

        386
      • For burst, step, block, and demand transfers

        386
      • For burst, step, and block transfers

        387
      • For a demand transfer

        387
  • 4. Operation Flowcharts

    389
  • 5. Data Bus

    392
  • 6. DMA External Interface

    395
    • 6.1 Input Timing of the DREQx Pin

      395
    • 6.2 FR30 Compatible Mode of DACK

      396
      • 2-cycle transfer mode

        396
      • Fly-by transfer mode

        397
• Chapter 27 Delayed Interrupt

  399
  • 1. Overview

    399
  • 2. Features

    399
  • 3. Configuration

    399
  • 4. Register

    400
    • 4.1 DICR: Delayed Interrupt Control Register

      400
  • 5. Operation

    400
  • 6. Setting

    401
  • 7. Q & A

    401
    • 7.1 What are interrupt-associated registers?

      401
    • 7.2 How is the interrupt request generated/cleared?

      401
  • 8. Caution

    401
• Chapter 28 Bit Search

  403
  • 1. Overview

    403
  • 2. Features

    403
  • 3. Configuration

    404
  • 4. Register

    405
    • 4.1 BSD0: 0 Detection Register / BSD1:1 Detection Register / BSDC: Changing position Detection Data Register

      405
    • 4.2 BSRR: Detection Result Register

      406
  • 5. Operation

    407
    • 5.1 Zero detection

      407
    • 5.2 One Detection

      407
    • 5.3 Changing Position Detection

      408
  • 6. Setting

    409
  • 7. Q & A

    410
    • 7.1 How is data written?

      410
    • 7.2 How is scanning started?

      410
    • 7.3 How is a result read?

      410
    • 7.4 How is the previous bit search state restored?

      410
  • 8. Caution

    411
• Chapter 29 MPU / EDSU

  413
  • 1. Overview

    413
  • 2. Features

    414
  • 3. Break Functions

    415
    • 3.1 Instruction address break

      415
    • 3.2 Operand address break

      416
    • 3.3 Data value break

      418
    • 3.4 Using operand with data break

      419
    • 3.5 Memory Protection

      420
    • 3.6 Break Factors

      421
  • 4. Registers

    423
    • 4.1 List of EDSU Registers

      423
    • 4.2 Explanations of Registers

      426
      • EDSU Control Register (BCTRL)

        426
      • EDSU Status Register (BSTAT)

        430
      • EDSU Instruction Address Capture Register (BIAC)

        433
      • EDSU Operand Address Capture Register (BOAC)

        433
      • EDSU Break Detection Interrupt Request Register (BIRQ)

        433
      • EDSU Channel Configuration Register (BCR0...BCR7)

        435
      • Break Address/Data register (BAD0...BAD31)

        443
  • 5. Quick Reference

    445
• Chapter 30 I/O Ports

  447
  • 1. I/O Ports Functions

    447
  • 2. I/O Circuit Types

    469
    • 2.1 I/O Cell List MB91V460

      469
    • 2.2 I/O Input Voltages (VIL/VIH)

      469
  • 3. Port Register Settings

    470
    • 3.1 General Rules

      470
    • 3.2 I/O Port Block Diagram

      472
    • 3.3 Port Input Enable

      473
    • 3.4 Port Function Register Setup

      474
    • 3.5 Port Input Level Selection

      514
    • 3.6 Programmable Pull-Up/Pull Down Resistors

      516
    • 3.7 Programmable Port Output Drive

      519
• Chapter 31 External Bus

  523
  • 1. Overview of the External Bus Interface

    523
    • 1.1 Features

      523
      • The external bus interface has the following features:

        523
      • In each chip select area, the following functions can be set independently:

        523
      • A different detailed timing can be set for each access timing type.

        523
      • Fly-by transfer by DMA can be performed.

        524
      • External bus arbitration using BRQ and BGRNT can be performed.

        524
      • Pins that are not used by the external interface can be used as general-purpose I/O ports through settings.

        524
    • 1.2 Block Diagram

      525
    • 1.3 I/O Pins

      526
      • Ordinary bus interface

        526
      • Memory interface

        526
      • DMA interface

        526
    • 1.4 Register List

      526
  • 2. External Bus Interface Registers

    528
    • 2.1 Area Select Registers 0-7(ASR0-7)

      528
    • 2.2 Area Configuration Registers 0-7 (ACR0-7)

      529
      • CS area mask setting function

        535
    • 2.3 Area Wait Register (AWR0-7)

      536
      • Memory type A(SDRAM/FCRAM) and Memory type B(FCRAM)

        542
    • 2.4 Memory setting register (MCRA for SDRAM/FCRAM auto - precharge OFF mode)

      544
    • 2.5 Memory setting register (MCRB for FCRAM auto - precharge ON mode)

      546
    • 2.6 I/O Wait Registers for DMAC (IOWR0-3)

      547
    • 2.7 Chip Select Enable Register (CSER)

      550
    • 2.8 Cache Enable Register (CHER)

      551
    • 2.9 Pin/Timing Control Register (TCR)

      552
    • 2.10 Refresh Control Register (RCR)

      554
  • 3. Setting Example of the Chip Select Area

    558
    • Example of setting ASRs and ASZ3-0

      558
  • 4. Endian and Bus Access

    559
    • Ordinary bus interface

      559
    • Time division I/O interface

      559
    • SDRAM Interface

      560
    • 4.1 Big Endian Bus Access

      560
      • Word access (when LD/ST instruction executed)

        560
      • 32-bit bus width

        561
      • 16-bit bus width

        562
      • 8-bit bus width

        562
      • 32-bit bus width

        563
      • 16-bit bus width

        563
      • 8-bit bus width

        564
    • 4.2 Little Endian Bus Access

      565
      • Word access

        565
      • Halfword access

        566
      • Byte access

        566
      • 32-bit bus width

        567
      • 16-bit bus width

        567
      • 8-bit bus width

        568
      • 32-bit bus width

        568
      • 16-bit bus width

        569
      • 8-bit bus width

        569
    • 4.3 Comparison of Big Endian and Little Endian External Access

      570
  • 5. Operation of the Ordinary bus interface

    578
    • 5.1 Basic Timing

      578
    • 5.2 Operation of WRn + Byte Control Type

      579
    • 5.3 Read -> Write Operation

      581
    • 5.4 Write -> Write Operation

      581
    • 5.5 Auto-Wait Cycle

      582
    • 5.6 External Wait Cycle

      583
    • 5.7 Synchronous Write Enable Output

      584
    • 5.8 CSn Delay Setting

      586
    • 5.9 CSn -> RD/WRn Setup and RD/WRn -> CSn Hold Setting

      587
    • 5.10 DMA Fly-By Transfer (I/O -> Memory)

      587
    • 5.11 DMA Fly-By Transfer (Memory -> I/O)

      588
  • 6. Burst Access Operation

    590
  • 7. Address/data Multiplex Interface

    592
  • 8. Prefetch Operation

    595
    • Basic conditions for starting external access using prefetch

      595
    • Optional clear for temporary stopping of a prefetch access

      595
    • Unit for one prefetch access operation

      595
    • Burst length setting and prefetch efficiency

      596
    • Reading from the prefetch buffer

      596
    • Clearing/updating the prefetch buffer

      596
    • Restrictions on prefetch-enabled areas

      597
  • 9. SDRAM/FCRAM Interface Operation

    598
    • 9.1 Self Refresh

      600
      • Self - refresh mode transition procedure

        601
      • Self - refresh mode reset procedure

        601
    • 9.2 Power-on Sequence

      601
    • 9.3 Connecting SDRAM/FCRAM to Many Areas

      602
    • 9.4 Address Multiplexing Format

      602
    • 9.5 Memory Connection Example

      603
      • Using 8 - bit SDRAM/FCRAM (Big endian)

        604
      • Using 16 - bit SDRAM/FCRAM

        605
      • Using 32 - bit SDRAM

        606
  • 10. DMA Access Operation

    608
    • 10.1 DMA Fly-By Transfer (I/O -> Memory)

      608
    • 10.2 DMA Fly-By Transfer (Memory -> I/O)

      610
    • 10.3 DMA Fly-By Transfer (I/O -> SDRAM/FCRAM)

      611
    • 10.4 DMA Fly-By Transfer (SDRAM/FCRAM -> I/O)

      613
      • At SDRAM page hit (Shortest)

        614
      • At SDRAM page misses

        615
    • 10.5 2-Cycle Transfer (Internal RAM -> External I/O, RAM)

      618
    • 10.6 2-Cycle Transfer (External -> I/O)

      618
    • 10.7 2-Cycle Transfer (I/O -> External)

      619
    • 10.8 2-Cycle Transfer (I/O -> SDRAM/FCRAM)

      620
    • 10.9 2-Cycle Transfer (SDRAM/FCRAM -> I/O)

      621
  • 11. Bus Arbitration

    624
  • 12. Procedure for Setting a Register

    626
  • 13. Notes on Using the External Bus Interface

    627
• Chapter 32 USART (LIN / FIFO)

  629
  • 1. Overview

    629
  • 2. USART Configuration

    632
  • 3. USART Pins

    636
  • 4. USART Registers

    637
    • 4.1 Serial Control Register 04 (SCR04)

      637
    • 4.2 Serial Mode Register 04 (SMR04)

      640
    • 4.3 Serial Status Register 04 (SSR04)

      641
    • 4.4 Reception and Transmission Data Register (RDR04 / TDR04)

      644
    • 4.5 Extended Status/Control Register (ESCR04)

      645
    • 4.6 Extended Communication Control Register (ECCR04)

      646
    • 4.7 Baud Rate / Reload Counter Register 0 and 1 (BGR04 / 14)

      648
    • 4.8 FIFO Control Register (FCR04)

      650
    • 4.9 FIFO Status Register (FSR04)

      652
  • 5. USART Interrupts

    654
    • 5.1 Reception Interrupt Generation and Flag Set Timing

      656
    • 5.2 Transmission Interrupt Generation and Flag Set Timing

      657
  • 6. USART Baud Rates

    658
    • 6.1 Setting the Baud Rate

      659
    • 6.2 Restarting the Reload Counter

      661
  • 7. USART Operation

    663
    • 7.1 Operation in Asynchronous Mode (Op. Modes 0 and 1)

      664
    • 7.2 Operation in Synchronous Mode (Operation Mode 2)

      665
    • 7.3 Operation with LIN Function (Operation Mode 3)

      668
    • 7.4 Direct Access to Serial Pins

      670
    • 7.5 Bidirectional Communication Function (Normal Mode)

      671
    • 7.6 Master-Slave Communication Function (Multiprocessor Mode)

      671
    • 7.7 LIN Communication Function

      675
    • 7.8 Sample Flowcharts for USART in LIN Communication (Operation Mode 3)

      675
  • 8. Notes on using USART

    679
• Chapter 33 I2C Controller

  681
  • 1. Overview

    681
  • 2. I2C Interface Registers

    683
    • 2.1 Bus Control Register (IBCR0)

      685
    • 2.2 Bus Status Register (IBSR0)

      689
    • 2.3 Ten Bit Slave Address Register (ITBA0)

      692
    • 2.4 Ten Bit Address Mask Register (ITMK0)

      693
    • 2.5 Seven Bit Slave Address Register (ISBA0)

      695
    • 2.6 Seven Bit Slave Address Mask Register (ISMK0)

      696
    • 2.7 Data Register (IDAR0)

      697
    • 2.8 Clock Control Register (ICCR0)

      698
  • 3. I2C Interface Operation

    701
  • 4. Programming Flow Charts

    703
• Chapter 34 CAN Controller

  707
  • 1. Overview

    707
  • 2. Register Description

    708
    • 2.1 Programmer’s Model

      708
    • 2.2 Hardware Reset Description

      711
    • 2.3 CAN Protocol Related Registers

      712
    • 2.4 Message Interface Register Sets

      720
    • 2.5 Message Object in the Message Memory

      727
    • 2.6 Message Handler Registers

      730
  • 3. Functional Description

    736
    • 3.1 Software Initialisation

      736
    • 3.2 CAN Message Transfer

      736
    • 3.3 Disabled Automatic Retransmission

      736
    • 3.4 Test Mode

      737
    • 3.5 Silent Mode

      737
    • 3.6 Loop Back Mode

      737
    • 3.7 Loop Back combined with Silent Mode

      738
    • 3.8 Basic Mode

      738
    • 3.9 Software control of Pin CAN_TX

      739
  • 4. CAN Application

    740
    • 4.1 Management of Message Objects

      740
    • 4.2 Message Handler State Machine

      740
    • 4.3 Data Transfer from/to Message RAM

      740
    • 4.4 Transmission of Messages

      741
    • 4.5 Acceptance Filtering of Received Messages

      742
    • 4.6 Reception of Data Frame

      742
    • 4.7 Reception of Remote Frame

      742
    • 4.8 Receive / Transmit Priority

      742
    • 4.9 Configuration of a Transmit Object

      742
    • 4.10 Updating a Transmit Object

      743
    • 4.11 Configuration of a Receive Object

      743
    • 4.12 Handling of Received Messages

      744
    • 4.13 Configuration of a FIFO Buffer

      744
    • 4.14 Reception of Messages with FIFO Buffers

      744
    • 4.15 Reading from a FIFO Buffer

      745
    • 4.16 Handling of Interrupts

      745
    • 4.17 Bit Time and Bit Rate

      746
• Chapter 35 Free-Run Timer

  749
  • 1. Overview

    749
  • 2. Features

    749
  • 3. Configuration Diagram

    750
  • 4. Registers

    751
    • 4.1 TCCS: Timer Control Register

      751
    • 4.2 TCDT: Timer Data Register

      754
  • 5. Operation

    755
    • 5.1 Count Operation of the Free-run Timer

      755
    • 5.2 Various Clear Operations of the Free-run Timer

      756
  • 6. Setting

    757
  • 7. Q & A

    758
    • 7.1 What are the types of the internal clock, and how do I select?

      758
    • 7.2 How do I select the external clock?

      758
    • 7.3 How do I enable / disable the count operation of the free-run timer?

      758
    • 7.4 How do I clear the free-run timer?

      759
    • 7.5 What interrupt registers are used?

      759
    • 7.6 Interrupt Types

      759
    • 7.7 How do I enable interrupts?

      759
    • 7.8 How do I stop the free-run timer?

      760
    • 7.9 How are the free-run timer assigned to ICU and OCU?

      760
  • 8. Caution

    761
• Chapter 36 Input Capture

  763
  • 1. Overview

    763
  • 2. Features

    763
  • 3. Configuration

    764
  • 4. Register

    765
    • 4.1 IPCP: Input Capture Data Register

      765
    • 4.2 ICS: Input Capture Control Register

      766
  • 5. Operation

    768
    • 5.1 Capture Timing, Interrupt Timing

      768
    • 5.2 Input Capture Edge Specification and Operation

      769
  • 6. Settings

    770
  • 7. Q&A

    771
    • 7.1 What are the varieties of active edge polarity for external input, and how do I select them?

      771
    • 7.2 What about setting the external input pins (ICU0-7)?

      771
    • 7.3 What about interrupt-related registers?

      771
    • 7.4 What are the types of interrupts?

      772
    • 7.5 How do I enable interrupts?

      772
    • 7.6 How do I measure the pulse width of the input signal?

      773
  • 8. Caution

    774
• Chapter 37 Output Compare

  775
  • 1. Overview

    775
  • 2. Features

    775
  • 3. Configuration Diagram

    776
  • 4. Registers

    777
    • 4.1 OCS: Output Control Register

      777
    • 4.2 OCCP: Compare Register

      780
  • 5. Operation

    781
    • 5.1 Output Compare Output (Independent Reversal) CMODE=“0”

      781
    • 5.2 Output Compare Output (Cooperative Reversal) CMODE=“1”

      782
  • 6. Settings

    783
  • 7. Q & A

    784
    • 7.1 How do I set the compare value?

      784
    • 7.2 How do I set the compare mode? (for OCU1, OCU3, OCU5, OCU7 output)

      784
    • 7.3 How do I enable/disable the compare operation?

      784
    • 7.4 How do I set the initial level of the compare pin output?

      785
    • 7.5 How do I set the output for compare pins OCU0-OCU7?

      786
    • 7.6 How do I clear the free-run timer?

      786
    • 7.7 How do I enable the compare operation?

      786
    • 7.8 How do I compare the free-run timer value with the compare register value and clear the free-run timer when they match?

      786
    • 7.9 What are the interrupt-related registers?

      786
    • 7.10 What are the types of interrupts?

      787
    • 7.11 How do I enable interrupts?

      788
    • 7.12 Compare value calculation procedure

      788
  • 8. Caution

    789
• Chapter 38 Reload Timer

  791
  • 1. Overview

    791
  • 2. Features

    791
  • 3. Configuration

    792
  • 4. Registers

    794
    • 4.1 TMCSR: Reload Timer Control Status Register

      794
    • 4.2 TMR: Timer Register

      797
    • 4.3 TMRLR: Reload register

      797
  • 5. Operation

    798
    • 5.1 Internal Clock/Reload Mode

      798
    • 5.2 Internal Clock/One-shot Mode

      799
    • 5.3 External Event Clock Reload Mode

      800
    • 5.4 External Event Clock/One-shot Mode

      801
    • 5.5 Operation during Reset

      801
    • 5.6 Operation during Sleep Mode

      801
    • 5.7 Operation during Stop Mode

      801
    • 5.8 Operation when Returning from Stop Mode

      802
    • 5.9 Status Transition

      802
  • 6. Setting

    803
  • 7. Q & A

    805
    • 7.1 What is the reload value setting (rewriting) procedure?

      805
    • 7.2 What are the kinds of count clocks and how are they selected?

      805
    • 7.3 How to I enable/disable the reload timer count operation?

      805
    • 7.4 How do I set the reload timer mode (reload/one-shot)?

      805
    • 7.5 How do I reverse the output level?

      805
    • 7.6 What are the kinds of triggers, and how do I select them?

      807
    • 7.7 What are the types of external event clock active edges and how do I select them?

      807
    • 7.8 How do I make a pin a TOT output pin?

      807
    • 7.9 How do I make the TIN pin into an external event input pin, or an external trigger input pin?

      807
    • 7.10 How do I generate an activation trigger?

      808
    • 7.11 What are the interrupt-related registers?

      808
    • 7.12 How do I enable interrupts?

      808
    • 7.13 How do I stop the reload timer?

      809
  • 8. Caution

    810
• Chapter 39 Programmable Pulse Generator

  811
  • 1. Overview

    811
  • 2. Features

    811
  • 3. Configuration

    813
  • 4. Registers

    815
    • 4.1 PCSR: PPG Cycle Setting Register

      815
    • 4.2 PDUT: PPG Duty Setting Register

      816
    • 4.3 PCN: PPG Control Status register

      817
    • 4.4 GCN1: General Control register 1

      820
    • 4.5 GCN2: General Control Register 2

      822
    • 4.6 PTMR: PPG Timer Register

      823
  • 5. Operation

    824
    • 5.1 PWM Operation

      824
    • 5.2 One-Shot Operation

      825
    • 5.3 Restart Operation

      826
  • 6. Setting

    827
  • 7. Q & A

    829
    • 7.1 How do I set (rewrite) a cycle and a duty?

      829
    • 7.2 How do I enable or disable PPG operations?

      829
    • 7.3 How do I set the PPG operation mode (PWM operation/one-shot operation)?

      829
    • 7.4 How do I get it restarted?

      829
    • 7.5 What count clocks are available and how are they selected?

      830
    • 7.6 How do I clamp the PPG pin output level?

      830
    • 7.7 What activation triggers are available and how are they selected?

      831
    • 7.8 How do I invert the output polarity?

      833
    • 7.9 How do I program a pin as a PPG output pin?

      833
    • 7.10 How do I generate an activation trigger?

      834
    • 7.11 How do I stop a PPG operation?

      834
    • 7.12 What interrupt registers are used?

      834
    • 7.13 What interrupts are available and how are they selected?

      836
    • 7.14 How do I enable, disable and clear interrupts?

      836
  • 8. Caution

    837
• Chapter 40 Pulse Frequency Modulator

  839
  • 1. PFM Overview

    839
  • 2. Reload Counter Registers

    842
    • P0TMCSR, P1TMCSR structure

      842
    • Functions of the P0TMCSR, P1TMCSR bits

      842
    • P0TMR, P1TMR structure

      844
    • P0TMRLR, P1TMRLR structure

      845
  • 3. Reload Counter Operation

    846
    • Counter activation and operation timing

      846
    • Underflow operation timing

      847
    • Counter state transitions

      848
  • 4. PFM Operation and Setting

    849
• Chapter 41 Up/Down Counter

  851
  • 1. Overview

    851
  • 2. Feature

    851
  • 3. Configuration

    852
  • 4. Register

    856
    • 4.1 UDCC: Counter Control Register

      856
    • 4.2 UDCS: Count Status Register

      859
    • 4.3 UDCR: Up/Down Counter Register

      861
    • 4.4 UDRC: Up/Down Reload/Compare Register

      862
  • 5. Operation

    864
    • 5.1 Timer Mode CMS[1:0]=“00”

      864
    • 5.2 Up/Down Count Mode CMS[1:0]=“01”

      865
    • 5.3 Up/Down Count Mode CMS[1:0]=“01”

      866
    • 5.4 Phase Difference Count Mode (Multiply by 2) CMS[1:0]=“10”

      867
    • 5.5 Phase Difference Count Mode (Multiply by 4) CMS[1:0]=“11”

      868
    • 5.6 Clear Timing

      869
    • 5.7 Reload Timing

      870
    • 5.8 Writing a Value to Counter

      870
  • 6. Setting

    871
  • 7. Q&A

    873
    • 7.1 How do I select a bit length (8 or 16) of Up/Down Counter?

      873
    • 7.2 What types of count modes are available and how are they set?

      873
    • 7.3 How do I select a count source for Up/Down Counter running in the timer mode?

      873
    • 7.4 How do I select the edge with which Up/Down Counter running in the Up/down count mode detects an input signal (AIN or BIN)?

      873
    • 7.5 How do I set a value to Up/Down Counter?

      873
    • 7.6 When the Up/Down Counter's count-up value agrees with the compare value (RCR[0:1]), how do I enable clearing of Up/Down Counter the next time when the counter counts up?

      873
    • 7.7 How do I enable reloading of the reload value (RCR[1:0]) to Up/Down Counter when Up/Down Counter is underflowed?

      874
    • 7.8 How do I clear Up/Down Counter?

      874
    • 7.9 How do I clear Up/Down Counter using the ZIN pin?

      874
    • 7.10 How do I control Up/Down Counter's count operation using the ZIN pin?

      874
    • 7.11 How do I enable/disable Up/Down Counter's count operation?

      875
    • 7.12 How do I know the previous count direction (the current rotation direction)?

      875
    • 7.13 How do I know count direction changes?

      875
    • 7.14 How do I know that a compare-match has occurred?

      875
    • 7.15 How do I know that an overflow or underflow has occurred?

      876
    • 7.16 How do I set the reload/compare value?

      876
    • 7.17 What are interrupt-related registers?

      876
    • 7.18 What interrupts are available and how are they selected?

      876
    • 7.19 How do I enable (select), disable or clear interrupts?

      877
  • 8. Caution

    878
• Chapter 42 Sound Generator

  879
  • 1. Overview

    879
  • 2. Block Diagram

    880
  • 3. Registers

    881
    • 3.1 Register Details

      882
• Chapter 43 Stepper Motor Controller

  887
  • 1. Overview

    887
  • 2. Registers

    888
    • 2.1 Registers for Stepping Motor Controller

      889
    • 2.2 PWM Control Register

      890
    • 2.3 PWM1&2 Compare Registers

      892
    • 2.4 PWM1&2 Selection Registers

      894
  • 3. Operation

    897
  • 4. Caution

    899
• Chapter 44 A/D Converter

  901
  • 1. Overview of A/D Converter

    901
  • 2. Block Diagram of A/D Converter

    902
  • 3. Registers of A/D Converter

    903
    • 3.1 A/D Enable Register (ADER)

      905
    • 3.2 A/D Control Status Register (ADCS)

      906
    • 3.3 Data Register (ADCR1, ADCR0)

      908
    • 3.4 Sampling Timer Setting Register (ADCT)

      909
    • 3.5 A/D Channel Setting Register (ADSCH, ADECH)

      910
  • 4. Operation of A/D Converter

    912
    • 4.1 Single-shot conversion mode

      913
    • 4.2 Scan conversion mode

      914
  • 5. Setting

    915
  • 6. Q & A

    917
    • 6.1 What conversion modes are available and how are they selected?

      917
    • 6.2 How do I specify a bit length?

      917
    • 6.3 How do I set a conversion time?

      918
    • 6.4 How do I enable analog pin input?

      918
    • 6.5 How do I enable analog pin input for Stepper Motor Controller?

      919
    • 6.6 To select how to activate the A/D converter

      919
    • 6.7 To activate the A/D converter

      920
    • 6.8 To verify the end of a conversion

      920
    • 6.9 How do I read a conversion value?

      920
    • 6.10 How do I force an A/D conversion operation to a stop?

      920
    • 6.11 What interrupt registers are used?

      921
    • 6.12 What interrupts are available?

      921
    • 6.13 How do I enable, disable, clear interrupts?

      921
  • 7. Caution

    922
• Chapter 45 D/A Converter

  925
  • 1. Overview

    925
  • 2. Features

    925
  • 3. Configuration

    926
  • 4. Registers

    927
    • 4.1 DADR: D/A Data Register

      927
    • 4.2 DACR: D/A Control Register

      927
  • 5. Operation

    929
  • 6. Setting

    930
  • 7. Q & A

    931
    • 7.1 Where should I set digital values?

      931
    • 7.2 How do I program the D/A pins for D/A output?

      931
    • 7.3 How do I enable or disable D/A output?

      931
    • 7.4 How do I activate a D/A conversion?

      931
    • 7.5 What is the formula used to work out the value necessary to produce an expected voltage?

      931
  • 8. Caution

    932
• Chapter 46 Alarm Comparator

  933
  • 1. Overview

    933
  • 2. Block Diagram

    933
  • 3. Alarm Comparator Control/Status Register (ACSR)

    934
  • 4. Operation Modes

    935
    • 4.1 Interrupt Mode (IEN=1)

      935
    • 4.2 Polling Mode (IEN=0)

      935
    • 4.3 Setting and Resetting of IRQ-Flagbit

      935
    • 4.4 Power Down Modes of the Alarm Comparator

      936
• Chapter 47 LCD Controller

  937
  • 1. Overview

    937
  • 2. Features

    937
  • 3. Configuration

    938
  • 4. Registers

    940
    • 4.1 LCR0: LCDC Control Register 0

      940
    • 4.2 VRAM: Data Memory for Display

      942
    • 4.3 LCR1: LCDC Control Register 1

      944
    • 4.4 LCDCMR: Common Pin Switching Register

      944
  • 5. Operation

    945
    • 5.1 LCD Controller/Driver (LCDC) Operation

      945
    • 5.2 1/2 Duty Cycle Output Waveform

      945
    • 5.3 1/3 Duty Cycle Output Waveform

      947
    • 5.4 1/4 Duty Cycle Output Waveform

      949
  • 6. Setting

    950
  • 7. Q&A

    951
    • 7.1 How do I specify pins as COM or SEG output pins?

      951
    • 7.2 How do I set VRM?

      953
    • 7.3 How do I set a frame period?

      953
    • 7.4 How do I set a duty cycle?

      954
    • 7.5 How do I control starting and stopping of LCD?

      954
    • 7.6 How do I enable or disable LCD display?

      954
    • 7.7 How do I enable LCD display even in the sub-stop mode?

      954
    • 7.8 How do I select internal or external divided resistors?

      954
    • 7.9 How do I select internal or external divided resistors?

      955
    • 7.10 How do I use external divided resistors to shut off the current when LCD is deactivated?

      955
  • 8. Caution

    956
• Chapter 48 Clock Monitor

  957
  • 1. Overview

    957
  • 2. Features

    957
  • 3. Configuration

    958
  • 4. Register

    959
    • 4.1 Clock Monitor Configuration Register

      959
  • 5. Operation

    961
  • 6. Settings

    962
  • 7. Q&A

    962
    • 7.1 How do I set an output terminal (MONCLK)?

      962
    • 7.2 How do I select an output frequency?

      962
    • 7.3 How do I enable/disable clock monitor output?

      962
  • 8. Caution

    963
• Chapter 49 Real-Time Clock

  965
  • 1. Overview

    965
  • 2. Features

    965
  • 3. Configuration

    966
  • 4. Registers

    967
    • 4.1 WTCR: RTC Control Register

      967
    • 4.2 WTBR: Sub-Second Registers

      970
    • 4.3 WTHR/WTMR/WTSR: Hour/Minute/Second Registers

      971
  • 5. Operation

    972
  • 6. Setting

    974
  • 7. Q&A

    975
    • 7.1 How do I set the count period of 1 second?

      975
    • 7.2 How do I initialize Real-time Clock?

      975
    • 7.3 How do I set or update time (hour/minute/second)?

      975
    • 7.4 How do I start or stop Real-time Clock's counting?

      975
    • 7.5 How do I confirm that Real-time Clock is active?

      975
    • 7.6 How do I know time?

      975
    • 7.7 How do I stop Real-time Clock?

      975
    • 7.8 What are interrupt-related registers?

      976
    • 7.9 What interrupts are available and how are they selected?

      976
    • 7.10 How do I enable interrupts?

      976
  • 8. Caution

    977
• Chapter 50 Subclock Calibration Unit

  979
  • 1. Overview

    979
    • 1.1 Description

      979
  • 2. Block Diagram

    980
  • 3. Timing

    981
  • 4. Clocks

    982
    • Clock ratio

      982
    • The input frequencies must not exceed the values given in Table 4-1 .

      982
  • 5. Register Description

    983
    • 5.1 Calibration Unit Control Register (CUCR)

      984
    • 5.2 32 kHz / 100 kHz Timer Data Register (16 bit) (CUTD)

      986
    • 5.3 4 MHz Timer Data Register (24 bits) (CUTR)

      988
  • 6. Application Note

    989
    • 32kHz

      989
    • 100kHz

      989
• Chapter 51 Low Voltage Reset/Interrupt

  991
  • 1. Overview

    991
  • 2. Features

    991
  • 3. Registers

    992
    • 3.1 LV Detection Control Registers

      992
• Chapter 52 Regulator Control

  995
  • 1. Overview

    995
  • 2. Features

    995
  • 3. Registers

    996
    • 3.1 Regulator Control Registers

      996
• Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM

  999
  • 1. Overview

    999
  • 2. Check for Boot Conditions

    999
    • 2.1 Evaluation Chip MB91V460

      999
    • 2.2 Flash devices of MB91460 series (MB91F46x)

      1001
    • 2.3 Internal Bootloader Description

      1003
  • 3. Registers modified by Boot ROM

    1004
    • 3.1 Evaluation Chip MB91V460

      1004
    • 3.2 Flash devices of MB91460 series

      1004
  • 4. Flash Access Mode Switching

    1005
  • 5. Bootloader Update Strategy

    1006
• Chapter 54 Flash Memory

  1009
  • 1. Overview

    1009
  • 2. Features

    1009
  • 3. Configuration

    1010
    • 3.1 Address conversion from CPU Mode to Flash Programming Mode

      1011
  • 4. Registers

    1012
  • 5. Access Modes

    1012
    • 5.1 Access from the FR-CPU

      1012
  • 6. Flash Access Mode Switching

    1013
    • 6.1 Flash Memory Mode

      1014
  • 7. Auto Algorithms

    1015
    • 7.1 Command Operation

      1015
    • 7.2 Auto Algorithm Commands

      1016
    • 7.3 Hardware Sequence Flag

      1019
    • 7.4 FLCR: Hardware Sequence Flag

      1020
    • 7.5 Sample Use of Hardware Sequence Flag

      1022
  • 8. Caution

    1023
• Chapter 55 Flash Security

  1025
  • 1. Overview

    1025
  • 2. Features

    1025
  • 3. Flash Security Vectors

    1026
    • 3.1 Vector addresses

      1026
    • 3.2 Security Vector FSV1

      1026
    • 3.3 Security Vector FSV2

      1028
  • 4. Register

    1029
    • 4.1 Flash Security Control Register

      1029
• Chapter 56 Electrical Specification

  1033