用户手册 — Fujitsu mb91192

目录

• CHAPTER 1 Overview of MB91191/ MB91192 Series

  15
  • 1.1 Feature of MB91191/MB91192 Series

    16
  • 1.2 Block Diagram of All MB91191/MB91192 Series

    18
  • 1.3 Package Dimension

    19
  • 1.4 Pin Assignment

    21
  • 1.5 Pin Function Description

    23
  • 1.6 I/O Circuit Type

    29
• CHAPTER 2 Handling Devices

  31
  • 2.1 Precautions When Handling Devices

    32
  • 2.2 Others

    36
• CHAPTER 3 CPU

  37
  • 3.1 Memory Space

    38
  • 3.2 CPU Architecture

    40
  • 3.3 Dedicated Registers

    43
    • 3.3.1 Program Status Register (PS)

      46
  • 3.4 General-purpose Register

    50
  • 3.5 Data Construction

    51
  • 3.6 Word Alignment

    52
  • 3.7 Memory Map

    53
  • 3.8 Overview of Instructions

    54
    • 3.8.1 Branch Command with Delay Slot

      56
    • 3.8.2 Branch Command without Delay Slot

      58
  • 3.9 EIT (Exception, Interruption, and Trap)

    59
    • 3.9.1 Interrupt Level of EIT

      60
    • 3.9.2 Interrupt Stack Operation

      61
    • 3.9.3 EIT Vector Table

      62
    • 3.9.4 Multiple EIT Processing

      63
    • 3.9.5 Operation of EIT

      65
  • 3.10 Reset Sequence

    69
  • 3.11 Memory Access Mode

    70
  • 3.12 Clock Generation Section (Low Power Consumption Mechanism)

    73
    • 3.12.1 Reset Factor Register (RSRR) and Watchdog Timer Cycle Control Register (WTCR)

      75
    • 3.12.2 Standby Control Register (STCR)

      77
    • 3.12.3 Timebase Timer Clear Register (CTBR)

      78
    • 3.12.4 Gear Control Register (GCR)

      79
    • 3.12.5 Watchdog Reset Generation Delay Register (WPR)

      81
    • 3.12.6 Reset Factor Retention

      82
    • 3.12.7 Stop Status

      84
    • 3.12.8 Sleep Status

      87
    • 3.12.9 State Transition in Standby Mode

      90
    • 3.12.10 Gear Function

      91
    • 3.12.11 Clock Series Diagram

      94
    • 3.12.12 Clock Series of Peripheral Resource

      95
    • 3.12.13 Watchdog Function

      96
• CHAPTER 4 External Bus Interface

  99
  • 4.1 Overview of External Bus Interface

    100
  • 4.2 Block Diagram

    101
  • 4.3 Area of Bus Interface

    102
  • 4.4 Bus Interface

    103
  • 4.5 Register of External bus Interface

    104
    • 4.5.1 Area Selection Register (ASR) and Area Mask Register (AMR)

      105
    • 4.5.2 Area Mode Register 1 (AMD1)

      108
    • 4.5.3 Little Endian Register (LER)

      110
  • 4.6 Bus Operation

    111
    • 4.6.1 Relationship between Data Bus Width and Control Signal

      112
    • 4.6.2 Bus Access of Big Endian

      113
    • 4.6.3 Bus Access of Little Endian

      118
    • 4.6.4 Comparison between Big Endian and Little Endian for External Access

      122
  • 4.7 Bus Timing

    126
  • 4.8 Program Example of External Bus Operation

    127
• CHAPTER 5 I/O Port

  131
  • 5.1 Overview of I/O Port

    132
  • 5.2 Port 0

    133
  • 5.3 Port 1

    135
  • 5.4 Port 2, 3

    137
  • 5.5 Port 5

    139
  • 5.6 Port 6, 7

    141
  • 5.7 Port 4, 8, 9

    145
  • 5.8 Port A, B

    149
  • 5.9 Port C, D

    151
• CHAPTER 6 FG Input

  155
  • 6.1 Overview of FG Input

    156
  • 6.2 Capstan Input

    157
  • 6.3 Drum Input

    162
  • 6.4 Reel Input

    166
• CHAPTER 7 FRC Capture

  171
  • 7.1 Overview of FRC Capture

    172
  • 7.2 Register of FRC Capture

    174
  • 7.3 Operation of FRC Capture

    179
• CHAPTER 8 Programmable Pulse Generator (PPG0, 1)

  181
  • 8.1 Overview of Programmable Pulse Generator (PPG0, 1)

    182
  • 8.2 Register of Programmable Pulse Generator (PPG0, 1)

    185
  • 8.3 PPG Data RAM

    187
  • 8.4 Configuration of Frame Data

    188
  • 8.5 Operation of PPG

    189
• CHAPTER 9 Real Timing Generator (RTG)

  191
  • 9.1 Overview of Real Timing Generator (RTG)

    192
  • 9.2 Register of Real Timing Generator (RTG)

    195
  • 9.3 Operation of Real Timing Generator (RTG)

    197
• CHAPTER 10 Timer

  199
  • 10.1 Overview of Timer

    200
  • 10.2 Overview of 16-bit Timer (Timer 0 to 4)

    202
  • 10.3 Register of 16-bit Timer (Timer 0 to 4)

    204
  • 10.4 Operation of 16-bit Timer (Timer 0 to 4)

    207
  • 10.5 Overview of 8-/16-bit Timer/Counter

    209
  • 10.6 Register of 8-/16-bit Timer/Counter

    211
  • 10.7 Operation of 8-/16-bit Timer/Counter

    215
• CHAPTER 11 12-bit PWM

  217
  • 11.1 Overview of 12-bit PWM

    218
  • 11.2 Register of 12-bit PWM

    220
  • 11.3 Operation of 12-bit PWM

    222
• CHAPTER 12 8-bit Pulse Width Counter

  225
  • 12.1 Overview of 8-bit Pulse Width Counter

    226
  • 12.2 Register of 8-bit Pulse Width Counter

    227
  • 12.3 Operation of 8-bit Pulse Width Counter

    229
• CHAPTER 13 External Interrupt

  231
  • 13.1 Overview of External Interrupt

    232
  • 13.2 External Interrupt 1 (Key Input Circuit)

    233
  • 13.3 External Interrupt (INT0 to 2)

    235
• CHAPTER 14 Delayed Interrupt Module

  239
  • 14.1 Overview of Delayed Interrupt Module

    240
  • 14.2 Delayed Interrupt Control Register (DICR)

    241
  • 14.3 Operation of Delayed Interrupt Module

    242
• CHAPTER 15 Interrupt Controller

  243
  • 15.1 Overview of Interrupt Controller

    244
  • 15.2 Interrupt Control Register (ICRxx)

    246
  • 15.3 Operation of Interrupt Controller

    247
• CHAPTER 16 10-bit A/D Converter

  251
  • 16.1 Overview of 10-bit A/D Converter

    252
  • 16.2 Register of 10-bit A/D Converter

    253
  • 16.3 Operation of 10-bit A/D Converter

    259
  • 16.4 State Transition of 10-bit A/D Converter

    261
• CHAPTER 17 Serial I/O

  263
  • 17.1 Overview of Serial I/O

    264
  • 17.2 Register of Serial I/O

    266
  • 17.3 Serial Data RAM

    270
  • 17.4 Operation of Serial I/O

    271
• CHAPTER 18 10-bit General-purpose Prescaler

  275
  • 18.1 Overview of 10-bit General-purpose Prescaler

    276
  • 18.2 Register of 10-bit General-purpose Prescaler

    277
  • 18.3 Operation of 10-bit General-purpose Prescaler

    279
• CHAPTER 19 Bit Search Module

  281
  • 19.1 Overview of Bit Search Module

    282
  • 19.2 Register of Bit Search Module

    283
  • 19.3 Operation of Bit Search Module

    285
• CHAPTER 20 Wait Controller

  289
  • 20.1 Outline of Wait Control Section

    290
  • 20.2 Wait Control Register (WAITC)

    291
• CHAPTER 21 Flash Memory

  293
  • 21.1 Overview of Flash Memory

    294
  • 21.2 Flash Memory Status Register (FSTR)

    298
  • 21.3 Operation of Flash Memory

    300
  • 21.4 Flash Memory Auto Algorithm (Embedded Algorithm TM)

    302
  • 21.5 Auto Algorithm Execute State

    306
• Appendix

  311
  • Appendix A I/O Map

    312
  • Appendix B Interrupt vector

    320
  • Appendix C Measurement accuracy of peripheral circuit

    322
  • Appendix D Restrictions for Using MB91191/MB91192 series

    323
  • Appendix E Instruction List

    324
    • E.1 Instruction list of FR series

      328
      • Numerics

        341
      • A

        341
      • B

        341
      • C

        341
      • D

        342
      • E

        342
      • F

        342
      • G

        342
      • H

        342
      • I

        342
      • K

        343
      • L

        343
      • M

        343
      • N

        343
      • O

        343
      • P

        343
      • R

        344
      • S

        344
      • T

        344
      • U

        345
      • V

        345
      • W

        345