用户手册目录Front Cover1FOR SAFE OPERATION2Revision History3Preface5Important Alert Items9Manual Organization11Contents13Illustrations18CHAPTER 1 Device Overview211.1 Features221.1.1 Functions and performance221.1.2 Adaptability221.1.3 Interface231.2 Device Specifications241.2.1 Specifications summary241.2.2 Model and product number251.3 Power Requirements251.4 Environmental Specifications281.5 Acoustic Noise291.6 Shock and Vibration291.7 Reliability301.8 Error Rate311.9 Media Defects311.10Load/Unload Function311.11Advanced Power Management32CHAPTER 2 Device Configuration352.1 Device Configuration362.2 System Configuration372.2.1 ATA interface372.2.2 1 drive connection372.2.3 2 drives connection38CHAPTER 3 Installation Conditions393.1 Dimensions403.2 Mounting413.3 Cable Connections473.3.1 Device connector473.3.2 Cable connector specifications483.3.3 Device connection483.3.4 Power supply connector (CN1)493.4 Jumper Settings493.4.1 Location of setting jumpers493.4.2 Factory default setting503.4.3 Master drive-slave drive setting503.4.4 CSEL setting513.4.5 Power Up in Standby setting52CHAPTER 4 Theory of Device Operation534.1 Outline544.2 Subassemblies544.2.1 Disk544.2.2 Spindle544.2.3 Actuator544.2.4 Air filter554.3 Circuit Configuration554.4 Power-on Sequence584.5 Self-calibration594.5.1 Self-calibration contents594.5.2 Execution timing of self-calibration604.5.3 Command processing during self-calibration614.6 Read/write Circuit614.6.1 Read/write preamplifier (PreAmp)614.6.2 Write circuit614.6.3 Read circuit634.6.4 Digital PLL circuit644.7 Servo Control654.7.1 Servo control circuit654.7.2 Data-surface servo format684.7.3 Servo frame format704.7.4 Actuator motor control714.7.5 Spindle motor control72CHAPTER 5 Interface755.1 Physical Interface765.1.1 Interface signals765.1.2 Signal assignment on the connector775.2 Logical Interface805.2.1 I/O registers815.2.2 Command block registers825.2.3 Control block registers875.3 Host Commands885.3.1 Command code and parameters885.3.2 Command descriptions925.3.3 Error posting1815.4 Command Protocol1835.4.1 PIO Data transferring commands from device to host1835.4.2 PIO Data transferring commands from host to device1855.4.3 Commands without data transfer1875.4.4 Other commands1895.4.5 DMA data transfer commands1895.5 Ultra DMA Feature Set1925.5.1 Overview1925.5.2 Phases of operation1935.5.3 Ultra DMA data in commands1935.5.4 Ultra DMA data out commands1985.5.5 Ultra DMA CRC rules2025.5.6 Series termination required for Ultra DMA2035.6 Timing2045.6.1 PIO data transfer2045.6.2 Multiword data transfer2055.6.3 Ultra DMA data transfer2065.6.4 Power-on and reset219CHAPTER 6 Operations2216.1 Device Response to the Reset2226.1.1 Response to power-on2226.1.2 Response to hardware reset2236.1.3 Response to software reset2256.1.4 Response to diagnostic command2266.2 Power Save2276.2.1 Power save mode2276.2.2 Power commands2296.3 Defect Processing2296.3.1 Spare area2296.3.2 Alternating processing for defective sectors2306.4 Read-ahead Cache2326.4.1 DATA buffer structure2326.4.2 Caching operation2336.4.3 Using the read segment buffer2356.5 Write Cache2396.5.1 Cache operation239Glossary243Acronyms and Abbreviations247Index249Comment Form251Back Cover256文件大小: 1.7 MB页数: 256Language: English打开用户手册