用户手册目录Front Cover1FOR SAFE OPERATION2Revision History3Preface5Important Alert Items9Manual Organization11Contents13Illustrations19Figures19Tables21CHAPTER 1 Device Overview231.1 Features241.1.1 Functions and performance241.1.2 Adaptability241.1.3 Interface251.2 Device Specifications261.2.1 Specifications summary261.2.2 Model and product number271.3 Power Requirements281.4 Environmental Specifications301.5 Acoustic Noise311.6 Shock and Vibration311.7 Reliability321.8 Error Rate331.9 Media Defects331.10 Load/Unload Function331.11 Advanced Power Management341.12 Interface Power Management (IPM)361.12.1 Host-initiated Interface Power Management (HIPM)361.12.2 Device-initiated Interface Power Management (DIPM)36CHAPTER 2 Device Configuration392.1 Device Configuration402.2 System Configuration412.2.1 SATA interface412.2.2 Drive connection41CHAPTER 3 Installation Conditions433.1 Dimensions443.2 Mounting453.3 Connections with Host System513.3.1 Device connector513.3.2 Signal segment and power supply segment523.3.3 Connector specifications for host system523.3.4 SATA interface cable connection533.3.5 Note about SATA interface cable connection53CHAPTER 4 Theory of Device Operation554.1 Outline564.2 Subassemblies564.2.1 Disk564.2.2 Spindle564.2.3 Actuator564.2.4 Air filter574.3 Circuit Configuration574.4 Power-on Sequence604.5 Self-calibration614.5.1 Self-calibration contents614.5.2 Execution timing of self-calibration624.5.3 Command processing during self-calibration624.6 Read/write Circuit634.6.1 Read/write preamplifier (PreAMP)634.6.2 Write circuit634.6.3 Read circuit644.6.4 Digital PLL circuit654.7 Servo Control664.7.1 Servo control circuit664.7.2 Data-surface servo format684.7.3 Servo frame format704.7.4 Actuator motor control714.7.5 Spindle motor control72CHAPTER 5 Interface755.1 Physical Interface765.1.1 Interface signals765.1.2 Signal interface regulation785.1.3 Electrical specifications805.1.4 Connector pinouts825.2 Logical Interface835.2.1 Communication layers845.2.2 Outline of the Shadow Block Register855.2.3 Outline of the frame information structure (FIS)865.2.4 Shadow block registers915.3 Host Commands965.3.1 Command code and parameters965.3.2 Command descriptions995.3.3 Error posting2135.4 Command Protocol2155.4.1 Non-data command protocol2155.4.2 PIO data-in command protocol2175.4.3 PIO data-out command protocol2185.4.4 DMA data-in command protocol2205.4.5 DMA data-out command protocol2215.4.6 Native Command Queuing protocol2225.5 Power-on and COMRESET225CHAPTER 6 Operations2276.1 Reset and Diagnosis2286.1.1 Response to power-on2286.1.2 Response to COMRESET2306.1.3 Response to a software reset2316.2 Power Save2326.2.1 Power save mode2326.2.2 Power commands2346.3 Interface Power Save2356.3.1 Power save mode of the interface2356.4 Read-ahead Cache2376.4.1 Data buffer structure2376.4.2 Caching operation2386.4.3 Using the read segment buffer2406.5 Write Cache2446.5.1 Cache operation244Glossary247Acronyms and Abbreviations249Index251Comment Form259Back Cover264文件大小: 1.3 MB页数: 264Language: English打开用户手册