用户手册 — Fujitsu MPG3204AH

目录

• COVER

  1
• REVISION RECORD

  2
• MANUAL ORGANIZATION

  4
• PREFACE

  6
• CONTENTS

  10
• FIGURES

  14
• TABLES

  16
• CHAPTER 1 DEVICE OVERVIEW

  18
  • 1.1 Features

    18
    • 1.1.1 Functions and performance

      18
    • 1.1.2 Adaptability

      19
    • 1.1.3 Interface

      19
  • 1.2 Device Specifications

    21
    • 1.2.1 Specifications summary

      21
    • 1.2.2 Model and product number

      22
  • 1.3 Power Requirements

    22
  • 1.4 Environmental Specifications

    25
  • 1.5 Acoustic Noise

    25
  • 1.6 Shock and Vibration

    26
  • 1.7 Reliability

    26
  • 1.8 Error Rate

    27
  • 1.9 Media Defects

    27
• CHAPTER 2 DEVICE CONFIGURATION

  28
  • 2.1 Device Configuration

    28
  • 2.2 System Configuration

    30
    • 2.2.1 ATA interface

      30
    • 2.2.2 1 drive connection

      30
    • 2.2.3 2 drives connection

      30
• CHAPTER 3 INSTALLATION CONDITIONS

  32
  • 3.1 Dimensions

    32
  • 3.2 Handling Cautions

    34
    • 3.2.1 General notes

      34
    • 3.2.2 Installation

      34
    • 3.2.3 Recommended equipments

      34
  • 3.3 Mounting

    35
  • 3.4 Cable Connections

    39
    • 3.4.1 Device connector

      39
    • 3.4.2 Cable connector specifications

      40
    • 3.4.3 Device connection

      40
    • 3.4.4 Power supply connector (CN1)

      41
    • 3.4.5 System configuration for Ultra DMA

      41
  • 3.5 Jumper Settings

    44
    • 3.5.1 Location of setting jumpers

      44
    • 3.5.2 Factory default setting

      45
    • 3.5.3 Jumper configuration

      45
• CHAPTER 4 THEORY OF DEVICE OPERATION

  48
  • 4.1 Outline

    48
  • 4.2 Subassemblies

    48
    • 4.2.1 Disk

      48
    • 4.2.2 Head

      49
    • 4.2.3 Spindle

      50
    • 4.2.4 Actuator

      50
    • 4.2.5 Air filter

      50
  • 4.3 Circuit Configuration

    51
  • 4.4 Power-on Sequence

    53
  • 4.5 Self-calibration

    55
    • 4.5.1 Self-calibration contents

      55
    • 4.5.2 Execution timing of self-calibration

      56
    • 4.5.3 Command processing during self-calibration

      56
  • 4.6 Read/write Circuit

    57
    • 4.6.1 Read/write preamplifier (PreAMP)

      57
    • 4.6.2 Write circuit

      57
    • 4.6.3 Read circuit

      58
    • 4.6.4 Synthesizer circuit

      59
  • 4.7 Servo Control

    59
    • 4.7.1 Servo control circuit

      60
    • 4.7.2 Data-surface servo format

      63
    • 4.7.3 Servo frame format

      63
    • 4.7.4 Actuator motor control

      65
    • 4.7.5 Spindle motor control

      66
• CHAPTER 5 INTERFACE

  68
  • 5.1 Physical Interface

    69
    • 5.1.1 Interface signals

      69
    • 5.1.2 Signal assignment on the connector

      70
  • 5.2 Logical Interface

    73
    • 5.2.1 I/O registers

      73
    • 5.2.2 Command block registers

      75
    • 5.2.3 Control block registers

      80
  • 5.3 Host Commands

    80
    • 5.3.1 Command code and parameters

      81
    • 5.3.2 Command descriptions

      83
    • 5.3.3 Error posting

      137
  • 5.4 Command Protocol

    138
    • 5.4.1 Data transferring commands from device to host

      138
    • 5.4.2 Data transferring commands from host to device

      140
    • 5.4.3 Commands without data transfer

      142
    • 5.4.4 Other commands

      143
    • 5.4.5 DMA data transfer commands

      143
  • 5.5 Ultra DMA feature set

    145
    • 5.5.1 Overview

      145
    • 5.5.2 Phases of operation

      146
    • 5.5.3 Ultra DMA data in commands

      146
      • 5.5.3.1Initiating an Ultra DMA data in burst

        146
      • 5.5.3.2The data in transfer

        147
      • 5.5.3.3Pausing an Ultra DMA data in burst

        147
      • 5.5.3.4Terminating an Ultra DMA data in burst

        148
    • 5.5.4 Ultra DMA data out commands

      150
      • 5.5.4.1Initiating an Ultra DMA data out burst

        150
      • 5.5.4.2The data out transfer

        151
      • 5.5.4.3Pausing an Ultra DMA data out burst

        151
      • 5.5.4.4Terminating an Ultra DMA data out burst

        152
    • 5.5.5 Ultra DMA CRC rules

      154
    • 5.5.6 Series termination required for Ultra DMA

      155
  • 5.6 Timing

    156
    • 5.6.1 PIO data transfer

      156
    • 5.6.2 Multiword data transfer

      157
    • 5.6.3 Ultra DMA data transfer

      158
      • 5.6.3.1Initiating an Ultra DMA data in burst

        158
      • 5.6.3.2Ultra DMA data burst timing requirements

        159
      • 5.6.3.3Sustained Ultra DMA data in burst

        162
      • 5.6.3.4Host pausing an Ultra DMA data in burst

        163
      • 5.6.3.5Device terminating an Ultra DMA data in burst

        164
      • 5.6.3.6Host terminating an Ultra DMA data in burst

        165
      • 5.6.3.7Initiating an Ultra DMA data out burst

        166
      • 5.6.3.8Sustained Ultra DMA data out burst

        167
      • 5.6.3.9Device pausing an Ultra DMA data out burst

        168
      • 5.6.3.10Host terminating an Ultra DMA data out burst

        169
      • 5.6.3.11Device terminating an Ultra DMA data in burst

        170
    • 5.6.4 Power-on and reset

      171
• CHAPTER 6 OPERATIONS

  172
  • 6.1 Device Response to the Reset

    172
    • 6.1.1 Response to power-on

      173
    • 6.1.2 Response to hardware reset

      174
    • 6.1.3 Response to software reset

      175
    • 6.1.4 Response to diagnostic command

      176
  • 6.2 Address Translation

    177
    • 6.2.1 Default parameters

      177
    • 6.2.2 Logical address

      178
  • 6.3 Power Save

    179
    • 6.3.1 Power save mode

      179
    • 6.3.2 Power commands

      181
  • 6.4 Defect Management

    181
    • 6.4.1 Spare area

      182
    • 6.4.2 Alternating defective sectors

      182
  • 6.5 Read-Ahead Cache

    184
    • 6.5.1 Data buffer configuration

      184
    • 6.5.2 Caching operation

      185
    • 6.5.3 Usage of read segment

      186
  • 6.6 Write Cache

    191
• ADDRESSES

  193
• COMMENT FORM

  194
• BACK

  195