用户手册 — IBM nec pd78p081(a2)

目录

• COVER

  1
• PREFACE

  7
• CHAPTER 1 OUTLINE

  24
  • 1.1 Features

    24
  • 1.2 Applications

    25
  • 1.3 Ordering Information

    25
  • 1.4 Quality Grade

    26
  • 1.5 Pin Configuration (Top View)

    27
  • 1.6 78K/0 Series Development

    32
  • 1.7 Block Diagram

    34
  • 1.8 Outline of Function

    35
  • 1.9 Differences between the uPD78081, 78082 and 78P083, the uPD78081(A), 78082(A) and 78P083(A), and the uPD78081(A2)

    36
• CHAPTER 2 PIN FUNCTION

  38
  • 2.1 Pin Function List

    38
    • 2.1.1 Normal operating mode pins

      38
    • 2.1.2 PROM programming mode pins ( uPD78P083 only)

      39
  • 2.2 Description of Pin Functions

    40
    • 2.2.1 P00 to P03 (Port 0)

      40
    • 2.2.2 P10 to P17 (Port 1)

      40
    • 2.2.3 P30 to P37 (Port 3)

      41
    • 2.2.4 P50 to P57 (Port 5)

      41
    • 2.2.5 P70 to P72 (Port 7)

      42
    • 2.2.6 P100 to P101 (Port 10)

      42
    • 2.2.7 AVREF

      43
    • 2.2.8 AVDD

      43
    • 2.2.9 AVSS

      43
    • 2.2.10 RESET#

      43
    • 2.2.11 X1 and X2

      43
    • 2.2.12 VDD

      43
    • 2.2.13 VSS

      43
    • 2.2.14 VPP ( uPD78P083 only)

      43
    • 2.2.15 IC (Mask ROM version only)

      44
    • 2.2.16 NC (44-pin plastic QFP versions only)

      44
  • 2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins

    45
• CHAPTER 3 CPU ARCHITECTURE

  48
  • 3.1 Memory Spaces

    48
    • 3.1.1 Internal program memory space

      51
    • 3.1.2 Internal data memory space

      52
    • 3.1.3 Special Function Register (SFR) area

      52
    • 3.1.4 Data memory addressing

      52
  • 3.2 Processor Registers

    56
    • 3.2.1 Control registers

      56
    • 3.2.2 General registers

      59
    • 3.2.3 Special Function Register (SFR)

      60
  • 3.3 Instruction Address Addressing

    63
    • 3.3.1 Relative addressing

      63
    • 3.3.2 Immediate addressing

      64
    • 3.3.3 Table indirect addressing

      65
    • 3.3.4 Register addressing

      66
  • 3.4 Operand Address Addressing

    67
    • 3.4.1 Implied addressing

      67
    • 3.4.2 Register addressing

      68
    • 3.4.3 Direct addressing

      69
    • 3.4.4 Short direct addressing

      70
    • 3.4.5 Special-Function Register (SFR) addressing

      72
    • 3.4.6 Register indirect addressing

      73
    • 3.4.7 Based addressing

      74
    • 3.4.8 Based indexed addressing

      75
    • 3.4.9 Stack addressing

      75
• CHAPTER 4 PORT FUNCTIONS

  76
  • 4.1 Port Functions

    76
  • 4.2 Port Configuration

    78
    • 4.2.1 Port 0

      78
    • 4.2.2 Port 1

      80
    • 4.2.3 Port 3

      81
    • 4.2.4 Port 5

      82
    • 4.2.5 Port 7

      83
    • 4.2.6 Port 10

      85
  • 4.3 Port Function Control Registers

    86
  • 4.4 Port Function Operations

    90
    • 4.4.1 Writing to input/output port

      90
    • 4.4.2 Reading from input/output port

      90
    • 4.4.3 Operations on input/output port

      90
• CHAPTER 5 CLOCK GENERATOR

  92
  • 5.1 Clock Generator Functions

    92
  • 5.2 Clock Generator Configuration

    92
  • 5.3 Clock Generator Control Register

    94
  • 5.4 System Clock Oscillator

    96
    • 5.4.1 Main system clock oscillator

      96
    • 5.4.2 Scaler

      98
  • 5.5 Clock Generator Operations

    99
  • 5.6 Changing CPU Clock Settings

    100
    • 5.6.1 Time required for CPU clock switchover

      100
    • 5.6.2 CPU clock switching procedure

      101
• CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

  102
  • 6.1 8-Bit Timer/Event Counters 5 and 6 Functions

    103
  • 6.2 8-Bit Timer/Event Counters 5 and 6 Configurations

    105
  • 6.3 8-Bit Timer/Event Counters 5 and 6 Control Registers

    107
  • 6.4 8-Bit Timer/Event Counters 5 and 6 Operations

    113
    • 6.4.1 Interval timer operations

      113
    • 6.4.2 External event counter operation

      116
    • 6.4.3 Square-wave output

      117
    • 6.4.4 PWM output operations

      119
  • 6.5 Cautions on 8-Bit Timer/Event Counters 5 and 6

    123
• CHAPTER 7 WATCHDOG TIMER

  126
  • 7.1 Watchdog Timer Functions

    126
  • 7.2 Watchdog Timer Configuration

    128
  • 7.3 Watchdog Timer Control Registers

    129
  • 7.4 Watchdog Timer Operations

    132
    • 7.4.1 Watchdog timer operation

      132
    • 7.4.2 Interval timer operation

      133
• CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT

  134
  • 8.1 Clock Output Control Circuit Functions

    134
  • 8.2 Clock Output Control Circuit Configuration

    135
  • 8.3 Clock Output Function Control Registers

    136
• CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT

  138
  • 9.1 Buzzer Output Control Circuit Functions

    138
  • 9.2 Buzzer Output Control Circuit Configuration

    138
  • 9.3 Buzzer Output Function Control Registers

    139
• CHAPTER 10 A/D CONVERTER

  142
  • 10.1 A/D Converter Functions

    142
  • 10.2 A/D Converter Configuration

    142
  • 10.3 A/D Converter Control Registers

    145
  • 10.4 A/D Converter Operations

    149
    • 10.4.1 Basic operations of A/D converter

      149
    • 10.4.2 Input voltage and conversion results

      151
    • 10.4.3 A/D converter operating mode

      152
  • 10.5 A/D Converter Cautions

    154
• CHAPTER 11 SERIAL INTERFACE CHANNEL 2

  158
  • 11.1 Serial Interface Channel 2 Functions

    158
  • 11.2 Serial Interface Channel 2 Configuration

    159
  • 11.3 Serial Interface Channel 2 Control Registers

    163
  • 11.4 Serial Interface Channel 2 Operation

    171
    • 11.4.1 Operation stop mode

      171
    • 11.4.2 Asynchronous serial interface (UART) mode

      173
    • 11.4.3 3-wire serial I/O mode

      186
• CHAPTER 12 INTERRUPT FUNCTION

  194
  • 12.1 Interrupt Function Types

    194
  • 12.2 Interrupt Sources and Configuration

    195
  • 12.3 Interrupt Function Control Registers

    198
  • 12.4 Interrupt Servicing Operations

    204
    • 12.4.1 Non-maskable interrupt request acknowledge operation

      204
    • 12.4.2 Maskable interrupt request acknowledge operation

      207
    • 12.4.3 Software interrupt request acknowledge operation

      210
    • 12.4.4 Multiple interrupt servicing

      210
    • 12.4.5 Interrupt request reserve

      214
• CHAPTER 13 STANDBY FUNCTION

  216
  • 13.1 Standby Function and Configuration

    216
    • 13.1.1 Standby function

      216
    • 13.1.2 Standby function control register

      217
  • 13.2 Standby Function Operations

    218
    • 13.2.1 HALT mode

      218
    • 13.2.2 STOP mode

      221
• CHAPTER 14 RESET FUNCTION

  224
  • 14.1 Reset Function

    224
• CHAPTER 15 uPD78P083

  228
  • 15.1 Memory Size Switching Register

    229
  • 15.2 PROM Programming

    230
    • 15.2.1 Operating modes

      230
    • 15.2.2 PROM write procedure

      232
    • 15.2.3 PROM reading procedure

      236
  • 15.3 Erasure Procedure ( uPD78P083DU Only)

    237
  • 15.4 Opaque Film Masking the Window ( uPD78P083DU Only)

    237
  • 15.5 Screening of One-Time PROM Versions

    237
• CHAPTER 16 INSTRUCTION

  238
  • 16.1 Legends Used in Operation List

    239
    • 16.1.1 Operand identifiers and description methods

      239
    • 16.1.2 Description of “operation” column

      240
    • 16.1.3 Description of “flag operation” column

      240
  • 16.2 Operation List

    241
  • 16.3 Instructions Listed by Addressing Type

    249
• APPENDIX A DEVELOPMENT TOOLS

  254
  • A.1 Language Processing Software

    256
  • A.2 PROM Programming Tools

    257
    • A.2.1 Hardware

      257
    • A.2.2 Software

      257
  • A.3 Debugging Tools

    258
    • A.3.1 Hardware

      258
    • A.3.2 Software (1/3)

      259
    • A.3.2 Software (2/3)

      260
    • A.3.2 Software (3/3)

      261
  • A.4 OS for IBM PC

    262
  • A.5 System-Upgrade Method from Other In-Circuit Emulators to 78K/0 Series In-Circuit Emulator

    263
• APPENDIX B EMBEDDED SOFTWARE

  266
  • B.1 Real-time OS

    267
  • B.2 Fuzzy Inference Development Support System

    268
• APPENDIX C REGISTER INDEX

  270
  • C.1 Register Index

    270
• APPENDIX D REVISION HISTORY

  272