Intel 1.40 GHz 份说明书

数据表 (RH80532NC017256)

Introduction
10
Overview
10
State of the Data
11
Terminology
11
References
12
Mobile Intel Celeron Processor Features
13
New Features in the Mobile Intel Celeron Processor
13
2.1.1 133-MHz PSB With AGTL Signaling
13
2.1.2 256-K On-die Integrated L2 Cache
13
2.1.3 Data Prefetch Logic
13
2.1.4 Differential Clocking
13
(0.13 µ) (in Micro-FCBGA and Micro-FCPGA Packages)
14
Power Management
14
2.2.1 Clock Control Architecture
14
2.2.2 Normal State
14
2.2.3 Auto Halt State
14
Table 1. New and Revised Mobile Intel Celeron Processor (0.13 µ) Signals
14
2.2.4 Quick Start State
15
Figure 1. Clock Control States
15
2.2.5 HALT/Grant Snoop State
16
2.2.6 Deep Sleep State
16
2.2.7 Operating System Implications of Low-power States
17
AGTL Signals
17
Mobile Intel Celeron Processor CPUID
17
Table 2. Clock State Characteristics
17
Table 3. Mobile Intel Celeron Processor CPUID
18
Table 4. Mobile Intel Celeron Processor CPUID Cache and TLB Descriptors
18
Electrical Specifications
19
Processor System Signals
19
Table 5. System Signal Groups
19
3.1.1 Power Sequencing Requirements
20
3.1.2 Test Access Port (TAP) Connection
20
Table 6. Recommended Resistors for Mobile Intel Celeron Processor Signals
20
3.1.3 Catastrophic Thermal Protection
21
3.1.4 Unused Signals
21
3.1.5 Signal State in Low-power States
21
System Bus Signals
21
CMOS and Open-drain Signals
21
Other Signals
22
Power Supply Requirements
22
3.2.1 Decoupling Guidelines
22
3.2.2 Voltage Planes
22
3.2.3 Voltage Identification
23
Figure 2. PLL RLC Filter
23
Table 7. Mobile Intel Celeron Processor VID Values
23
3.2.4 VTTPWRGD Signal Quality Specification
24
Transition Region
24
Transition Time
24
Figure 3. VTTPWRGD System-Level Connections
24
Table 8. VTTPWRGD Noise Specification
24
Table 9. VTTPWRGD Transition Time Specification
24
Noise
25
System Bus Clock and Processor Clocking
25
Figure 4. Noise Estimation
25
Maximum Ratings
26
DC Specifications
26
Table 10. Mobile Intel Celeron Processor Absolute Maximum Ratings
26
Table 11. Power Specifications for Mobile Intel Celeron Processor1
27
VID = 1.15 V
28
Sleep State: VID = 1.15 V
29
VID = 1.1 V
29
in the Deep Sleep State: VID = 1.1 V
30
Table 16. VCC Tolerances for the Mobile Intel Celeron Processor: VID = 1.40 V
31
VID = 1.40 V
32
Table 18. VCC Tolerances for the Mobile Intel Celeron Processor: VID = 1.45 V
33
VID = 1.45 V
34
Table 20. VCC Tolerances for the Mobile Intel Celeron Processor: VID = 1.50 V
35
VID = 1.50 V
36
Figure 5. Illustration of VCC Static and Transient Tolerances (VID = 1.15 V)
37
Setting = 1.15 V)
37
Figure 7. Illustration of VCC Static and Transient Tolerances (VID = 1.40 V)
38
Setting = 1.40 V)
39
Table 22. AGTL Signal Group DC Specifications
40
Table 23. AGTL Bus DC Specifications
40
AC Specifications
41
3.6.1 System Bus, Clock, APIC, TAP, CMOS, and Open-drain AC Specifications
41
Table 25. System Bus Clock AC Specifications (Differential)
42
Table 26. System Bus Clock AC Specifications (133 MHz, Single Ended)
43
Table 27. System Bus Clock AC Specifications (100 MHz, Single Ended)
43
Table 28. Valid Mobile Intel Celeron Processor Frequencies
44
Table 29. AGTL Signal Groups AC Specifications
45
Table 30. CMOS and Open-drain Signal Groups AC Specifications
45
Table 31. Reset Configuration AC Specifications and Power On/Power Down Timings
46
Table 32. APIC Bus Signal AC Specifications
47
Table 33. TAP Signal AC Specifications
48
Table 34. Quick Start/Deep Sleep AC Specifications
48
Figure 9. BCLK (Single Ended)/PICCLK/TCK Generic Clock Timing Waveform
49
Figure 10. Differential BCLK/BCLK# Waveform (Common Mode)
49
Figure 11. BCLK/BCLK# Waveform (Differential Mode)
50
Figure 12. Valid Delay Timings
50
Figure 13. Setup and Hold Timings
51
Figure 14. Cold/Warm Reset and Configuration Timings
51
Figure 15. Power-on Sequence and Reset Timings
52
Figure 16. Power Down Sequencing and Timings (VCC Leading)
53
Figure 17.Power Down Sequencing and Timings (VCCT Leading)
54
Figure 18.Test Timings (Boundary Scan)
55
Figure 19. Test Reset Timings
55
Figure 20.Quick Start/Deep Sleep Timing (BCLK Stopping Method)
56
Figure 21. Quick Start/Deep Sleep Timing (DPSLP# Assertion Method)
57
System Signal Simulations
58
Specifications
58
Table 35. BCLK (Differential) DC Specifications and AC Signal Quality Specifications
58
Table 36. BCLK (Single Ended) DC Specifications and AC Signal Quality Specifications
58
Figure 22. BCLK (Single Ended)/PICCLK Generic Clock Waveform
59
Table 37. PICCLK DC Specifications and AC Signal Quality Specifications
59
AGTL AC Signal Quality Specifications
60
Figure 23. Maximum Acceptable Overshoot/Undershoot Waveform
60
Non-AGTL Signal Quality Specifications
61
Processor Core
61
Processor Core
61
4.3.1 PWRGOOD, VTTPWRGD Signal Quality Specifications
62
VTTPWRGD Noise Parameter Specification
62
Core
62
Table 41. VTTPWRGD Noise Parameter Specification
62
VTTPWRGD Transition Parameter Recommendation
63
Transition Region
63
Transition Time
63
Noise
63
Table 42. VTTPWRGD Transition Parameter Recommendation
63
Figure 24. VTTPWRGD Noise Specification
64
Mechanical Specifications
65
Socketable Micro-FCPGA Package
65
Table 43. Socketable Micro-FCPGA Package Specification
65
Figure 25. Socketable Micro-FCPGA Package - Top and Bottom Isometric Views
66
Figure 26. Socketable Micro-FCPGA Package - Top and Side View
67
Figure 27. Socketable Micro-FCPGA Package - Bottom View
68
Surface Mount Micro-FCBGA Package
69
Table 44. Micro-FCBGA Package Mechanical Specifications
69
Figure 28. Micro-FCBGA Package – Top and Bottom Isometric Views
70
Figure 29. Micro-FCBGA Package – Top and Side Views
71
Figure 30. Micro-FCBGA Package - Bottom View
72
Signal Listings
73
Figure 31. Pin/Ball Map - Top View
73
Table 45. Signal Listing in Order by Pin/Ball Number
74
Table 46. Signal Listing in Order by Signal Name
77
Table 47. Voltage and No-Connect Pin/Ball Locations
79
VCC Thermal Specifications
80
Table 48. Power Specifications for Mobile Intel Celeron Processor
81
Thermal Diode
82
Table 49. Thermal Diode Interface
82
Table 50. Thermal Diode Specifications
82
Processor Initialization and Configuration
83
Description
83
7.1.1 Quick Start Enable
83
7.1.2 System Bus Frequency
83
7.1.3 APIC Enable
83
Clock Frequencies and Ratios
83
Processor Interface
84
Alphabetical Signal Reference
84
Table 51. BSEL[1:0] Encoding
86
Signal Summaries
94
Table 52. Input Signals
94
Table 53. Output Signals
94
Table 54. Input/Output Signals (Single Driver)
95
Table 55. Input/Output Signals (Multiple Driver)
95
Appendix A. PLL RLC Filter Specification
96
Introduction
96
Filter Specification
96
Recommendation for Mobile Systems
97
Figure 32. PLL Filter Specifications
97
Table 56. PLL Filter Inductor Recommendations
97
Table 57. PLL Filter Capacitor Recommendations
97
Comments
98
Table 58. PLL Filter Resistor Recommendations
98

文件大小：

1.9 MB
页数：

98
Language:

English

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数据表 (RH80532NC017256)

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