用户手册 (BX80623I52500)目录2nd Generation Intel® Core™ Processor Family Desktop1Contents3Tables7Revision History81 Introduction91.1 Processor Feature Details111.1.1 Supported Technologies111.2 Interfaces111.2.1 System Memory Support111.2.2 PCI Express*121.2.3 Direct Media Interface (DMI)131.2.4 Platform Environment Control Interface (PECI)141.2.5 Processor Graphics141.2.6 Intel® Flexible Display Interface (Intel® FDI)141.3 Power Management Support151.3.1 Processor Core151.3.2 System151.3.3 Memory Controller151.3.4 PCI Express*151.3.5 DMI151.3.6 Processor Graphics Controller151.4 Thermal Management Support151.5 Package161.6 Terminology161.7 Related Documents182 Interfaces192.1 System Memory Interface192.1.1 System Memory Technology Supported192.1.2 System Memory Timing Support202.1.3 System Memory Organization Modes212.1.3.1 Single-Channel Mode212.1.3.2 Dual-Channel Mode – Intel® Flex Memory Technology Mode212.1.4 Rules for Populating Memory Slots222.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)222.1.5.1 Just-in-Time Command Scheduling222.1.5.2 Command Overlap232.1.5.3 Out-of-Order Scheduling232.1.6 Memory Type Range Registers (MTRRs) Enhancement232.1.7 Data Scrambling232.2 PCI Express* Interface242.2.1 PCI Express* Architecture242.2.1.1 Transaction Layer252.2.1.2 Data Link Layer252.2.1.3 Physical Layer252.2.2 PCI Express* Configuration Mechanism262.2.3 PCI Express* Port262.2.4 PCI Express Lanes Connection272.3 Direct Media Interface (DMI)272.3.1 DMI Error Flow272.3.2 Processor/PCH Compatibility Assumptions272.3.3 DMI Link Down282.4 Processor Graphics Controller (GT)282.4.1 3D and Video Engines for Graphics Processing292.4.1.1 3D Engine Execution Units292.4.1.2 3D Pipeline292.4.1.3 Video Engine302.4.1.4 2D Engine302.4.2 Processor Graphics Display312.4.2.1 Display Planes312.4.2.2 Display Pipes322.4.2.3 Display Ports322.4.3 Intel Flexible Display Interface322.4.4 Multi-Graphics Controller Multi-Monitor Support322.5 Platform Environment Control Interface (PECI)332.6 Interface Clocking332.6.1 Internal Clocking Requirements333 Technologies353.1 Intel® Virtualization Technology353.1.1 Intel® VT-x Objectives353.1.2 Intel® VT-x Features363.1.3 Intel® VT-d Objectives363.1.4 Intel® VT-d Features373.1.5 Intel® VT-d Features Not Supported373.2 Intel® Trusted Execution Technology (Intel® TXT)383.3 Intel® Hyper-Threading Technology383.4 Intel® Turbo Boost Technology393.4.1 Intel® Turbo Boost Technology Frequency393.4.2 Intel® Turbo Boost Technology Graphics Frequency393.5 Intel® Advanced Vector Extensions (AVX)403.6 Advanced Encryption Standard New Instructions (AES-NI)403.6.1 PCLMULQDQ Instruction403.7 Intel® 64 Architecture x2APIC414 Power Management434.1 ACPI States Supported434.1.1 System States434.1.2 Processor Core/Package Idle States434.1.3 Integrated Memory Controller States444.1.4 PCIe Link States444.1.5 DMI States444.1.6 Processor Graphics Controller States444.1.7 Interface State Combinations454.2 Processor Core Power Management454.2.1 Enhanced Intel® SpeedStep® Technology454.2.2 Low-Power Idle States464.2.3 Requesting Low-Power Idle States474.2.4 Core C-states484.2.4.1 Core C0 State484.2.4.2 Core C1/C1E State484.2.4.3 Core C3 State484.2.4.4 Core C6 State484.2.4.5 C-State Auto-Demotion484.2.5 Package C-States494.2.5.1 Package C0504.2.5.2 Package C1/C1E514.2.5.3 Package C3 State514.2.5.4 Package C6 State514.3 IMC Power Management524.3.1 Disabling Unused System Memory Outputs524.3.2 DRAM Power Management and Initialization524.3.2.1 Initialization Role of CKE544.3.2.2 Conditional Self-Refresh544.3.2.3 Dynamic Power-down Operation544.3.2.4 DRAM I/O Power Management544.4 PCIe* Power Management544.5 DMI Power Management554.6 Graphics Power Management554.6.1 Intel® Rapid Memory Power Management (RMPM) (also know as CxSR)554.6.2 Intel® Graphics Performance Modulation Technology(GPMT)554.6.3 Graphics Render C-State554.6.4 Intel® Smart 2D Display Technology (Intel® S2DDT)554.6.5 Intel® Graphics Dynamic Frequency564.7 Thermal Power Management565 Thermal Management576 Signal Description596.1 System Memory Interface606.2 Memory Reference and Compensation616.3 Reset and Miscellaneous Signals626.4 PCI Express* Based Interface Signals636.5 Intel® Flexible Display Interface Signals636.6 DMI646.7 PLL Signals646.8 TAP Signals646.9 Error and Thermal Protection656.10 Power Sequencing656.11 Processor Power Signals666.12 Sense Pins666.13 Ground and NCTF666.14 Processor Internal Pull Up/Pull Down677 Electrical Specifications697.1 Power and Ground Lands697.2 Decoupling Guidelines697.2.1 Voltage Rail Decoupling697.3 Processor Clocking (BCLK[0], BCLK#[0])707.3.1 PLL Power Supply707.4 VCC Voltage Identification (VID)707.5 System Agent (SA) VCC VID747.6 Reserved or Unused Signals747.7 Signal Groups757.8 Test Access Port (TAP) Connection767.9 Storage Conditions Specifications777.10 DC Specifications787.10.1 Voltage and Current Specifications787.11 Platform Environmental Control Interface (PECI) DC Specifications847.11.1 PECI Bus Architecture847.11.2 DC Characteristics857.11.3 Input Device Hysteresis858 Processor Pin and Signal Information878.1 Processor Pin Assignments879 DDR Data Swizzling107文件大小: 765.5 KB页数: 110Language: English打开用户手册