用户手册 — Intel i5-2520M

目录

• Contents

  3
• 1 Features Summary

  10
  • 1.1 Introduction

    10
  • 1.2 Processor Feature Details

    12
    • 1.2.1 Supported Technologies

      12
  • 1.3 Interfaces

    12
    • 1.3.1 System Memory Support

      12
    • 1.3.2 PCI Express*

      13
    • 1.3.3 Direct Media Interface (DMI)

      14
    • 1.3.4 Platform Environment Control Interface (PECI)

      15
    • 1.3.5 Intel® HD Graphics Controller

      15
    • 1.3.6 Embedded DisplayPort* (eDP*)

      15
    • 1.3.7 Intel® Flexible Display Interface (Intel® FDI)

      16
  • 1.4 Power Management Support

    16
    • 1.4.1 Processor Core

      16
    • 1.4.2 System

      16
    • 1.4.3 Memory Controller

      16
    • 1.4.4 PCI Express*

      16
    • 1.4.5 DMI

      16
    • 1.4.6 Integrated Graphics Controller

      16
  • 1.5 Thermal Management Support

    17
  • 1.6 Package

    17
  • 1.7 Terminology

    17
  • 1.8 Related Documents

    19
• 2 Interfaces

  20
  • 2.1 System Memory Interface

    20
    • 2.1.1 System Memory Technology Supported

      20
    • 2.1.2 System Memory Timing Support

      21
    • 2.1.3 System Memory Organization Modes

      21
    • 2.1.4 Rules for Populating Memory Slots

      23
    • 2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)

      23
    • 2.1.6 DRAM Clock Generation

      24
    • 2.1.7 System Memory Pre-Charge Power Down Support Details

      24
  • 2.2 PCI Express Interface

    24
    • 2.2.1 PCI Express Architecture

      24
    • 2.2.2 PCI Express Configuration Mechanism

      26
    • 2.2.3 PCI Express Graphics

      27
  • 2.3 DMI

    27
    • 2.3.1 DMI Error Flow

      27
    • 2.3.2 Processor/PCH Compatibility Assumptions

      27
    • 2.3.3 DMI Link Down

      27
  • 2.4 Integrated Graphics Controller

    27
    • 2.4.1 3D and Video Engines for Graphics Processing

      28
    • 2.4.2 Integrated Graphics Display Pipes

      30
    • 2.4.3 Intel Flexible Display Interface

      32
  • 2.5 Platform Environment Control Interface (PECI)

    33
  • 2.6 Interface Clocking

    33
    • 2.6.1 Internal Clocking Requirements

      33
• 3 Technologies

  34
  • 3.1 Intel® Virtualization Technology (Intel® VT)

    34
    • 3.1.1 Intel® VT-x Objectives

      34
    • 3.1.2 Intel VT-x Features

      35
    • 3.1.3 Intel® VT-d Objectives

      35
    • 3.1.4 Intel VT-d Features Supported

      36
    • 3.1.5 Intel VT-d Features Not Supported

      36
  • 3.2 Intel® Trusted Execution Technology (Intel® TXT)

    37
  • 3.3 Intel® Hyper-Threading Technology

    37
  • 3.4 Intel® Turbo Boost Technology

    38
    • 3.4.1 Intel Turbo Boost Technology Processor Frequency

      38
    • 3.4.2 Intel HD Graphics with Dynamic Frequency

      38
  • 3.5 New Instructions

    39
    • 3.5.1 Advanced Encryption Standard New Instructions (AESNI)

      39
    • 3.5.2 PCLMULQDQ Instruction

      39
• 4 Power Management

  40
  • 4.1 ACPI States Supported

    40
    • 4.1.1 System States

      40
    • 4.1.2 Processor Core/Package Idle States

      40
    • 4.1.3 Integrated Memory Controller States

      41
    • 4.1.4 PCIe Link States

      41
    • 4.1.5 DMI States

      41
    • 4.1.6 Integrated Graphics Controller States

      41
    • 4.1.7 Interface State Combinations

      42
  • 4.2 Processor Core Power Management

    42
    • 4.2.1 Enhanced Intel SpeedStep® Technology

      43
    • 4.2.2 Low-Power Idle States

      43
    • 4.2.3 Requesting Low-Power Idle States

      44
    • 4.2.4 Core C-states

      45
    • 4.2.5 Package C-States

      46
  • 4.3 IMC Power Management

    49
    • 4.3.1 Disabling Unused System Memory Outputs

      49
    • 4.3.2 DRAM Power Management and Initialization

      49
  • 4.4 PCIe Power Management

    51
  • 4.5 DMI Power Management

    51
  • 4.6 Integrated Graphics Power Management

    51
    • 4.6.1 Intel® Display Power Saving Technology 5.0 (Intel® DPST 5.0)

      51
    • 4.6.2 Graphics Render C-State

      51
    • 4.6.3 Graphics Performance Modulation Technology

      51
    • 4.6.4 Intel® Smart 2D Display Technology (Intel® S2DDT)

      51
  • 4.7 Thermal Power Management

    52
• 5 Thermal Management

  53
  • 5.1 Thermal Design Power and Junction Temperature

    53
    • 5.1.1 Intel Turbo Boost Technology and Graphics Dynamic Frequency

      53
    • 5.1.2 Intel Turbo Boost Technology and Graphics Dynamic Frequency Thermal Design Considerations and Specifications

      54
    • 5.1.3 Idle Power Specifications

      56
    • 5.1.4 Intel Turbo Boost Technology Control Overview

      57
    • 5.1.5 Component Power Measurement/Estimation Error

      57
  • 5.2 Thermal Management Features

    58
    • 5.2.1 Processor Core Thermal Features

      58
    • 5.2.2 Integrated Graphics and Memory Controller Thermal Features

      63
    • 5.2.3 Platform Environment Control Interface (PECI)

      66
• 6 Signal Description

  68
  • 6.1 System Memory Interface

    69
  • 6.2 Memory Reference and Compensation

    71
  • 6.3 Reset and Miscellaneous Signals

    72
  • 6.4 PCI Express Graphics Interface Signals

    73
  • 6.5 Embedded DisplayPort (eDP)

    74
  • 6.6 Intel Flexible Display Interface Signals

    75
  • 6.7 DMI

    75
  • 6.8 PLL Signals

    76
  • 6.9 TAP Signals

    76
  • 6.10 Error and Thermal Protection

    77
  • 6.11 Power Sequencing

    78
  • 6.12 Processor Power Signals

    79
  • 6.13 Ground and NCTF

    81
  • 6.14 Processor Internal Pull Up/Pull Down

    82
• 7 Electrical Specifications

  83
  • 7.1 Power and Ground Pins

    83
  • 7.2 Decoupling Guidelines

    83
    • 7.2.1 Voltage Rail Decoupling

      83
  • 7.3 Processor Clocking (BCLK, BCLK#)

    83
    • 7.3.1 PLL Power Supply

      83
  • 7.4 Voltage Identification (VID)

    84
  • 7.5 Reserved or Unused Signals

    88
  • 7.6 Signal Groups

    89
  • 7.7 Test Access Port (TAP) Connection

    91
  • 7.8 Absolute Maximum and Minimum Ratings

    92
  • 7.9 Storage Conditions Specifications

    92
  • 7.10 DC Specifications

    93
    • 7.10.1 Voltage and Current Specifications

      94
  • 7.11 Platform Environmental Control Interface (PECI) DC Specifications

    103
    • 7.11.1 DC Characteristics

      103
    • 7.11.2 Input Device Hysteresis

      104
• 8 Processor Pin and Signal Information

  105
  • 8.1 Processor Pin Assignments

    105
  • 8.2 Package Mechanical Information

    178