数据表目录1 Introduction111.1 Terminology131.2 References141.3 State of Data152 Electrical Specifications172.1 Front Side Bus and GTLREF172.1.1 Front Side Bus Clock and Processor Clocking182.1.2 Front Side Bus Clock Select (BSEL[1:0])192.1.3 Phase Lock Loop (PLL) Power and Filter202.2 Voltage Identification (VID)212.3 Cache Voltage Identification (CVID)222.4 Reserved, Unused, and TESTHI Pins232.5 Mixing Processors242.6 Front Side Bus Signal Groups242.7 GTL+ Asynchronous and AGTL+ Asynchronous Signals262.8 Test Access Port (TAP) Connection272.9 Maximum Ratings272.10 Processor DC Specifications282.10.1 Flexible Motherboard (FMB) Guidelines282.10.2 VCC Overshoot Specification342.10.3 VCACHE Overshoot Specification352.10.4 Die Voltage Validation362.10.5 Clock, Miscellaneous and AGTL+ Specifications362.11 AGTL+ Front Side Bus Specifications403 Mechanical Specifications413.1 Package Mechanical Drawing423.2 Processor Component Keep-Out Zones453.3 Package Loading Specifications453.4 Package Handling Guidelines463.5 Package Insertion Specifications463.6 Processor Mass Specifications463.7 Processor Materials463.8 Processor Markings463.9 Processor Pin-Out Coordinates484 Pin Listing494.1 Dual-Core Intel® Xeon® Processor 7100 Series Pin Assignments494.1.1 Pin Listing by Pin Name494.1.2 Pin Listing by Pin Number575 Signal Definitions655.1 Signal Definitions656 Thermal Specifications736.1 Package Thermal Specifications736.1.1 Thermal Specifications736.1.2 Thermal Metrology776.2 Processor Thermal Features776.2.1 Thermal Monitor776.2.2 Thermal Monitor 2786.2.3 On-Demand Mode796.2.4 PROCHOT# Signal Pin806.2.5 FORCEPR# Signal Pin806.2.6 THERMTRIP# Signal Pin806.2.7 TCONTROL and Fan Speed Reduction806.2.8 Thermal Diode817 Features837.1 Power-On Configuration Options837.2 Clock Control and Low Power States837.2.1 Normal State847.2.2 HALT or Enhanced Power Down State847.2.3 Stop-Grant State857.2.4 Enhanced HALT Snoop State or HALT Snoop State, Stop Grant Snoop State867.3 Enhanced Intel SpeedStep® Technology867.4 System Management Bus (SMBus) Interface877.4.1 SMBus Device Addressing887.4.2 PIROM and Scratch EEPROM Supported SMBus Transactions907.4.3 Processor Information ROM (PIROM)907.4.4 Checksums1097.4.5 Scratch EEPROM1107.4.6 SMBus Thermal Sensor1107.4.7 Thermal Sensor Supported SMBus Transactions1117.4.8 SMBus Thermal Sensor Registers1137.4.9 SMBus Thermal Sensor Alert Interrupt1168 Boxed Processor Specifications1178.1 Introduction1178.2 Mechanical Specifications1188.2.1 Boxed Processor Heatsink Dimensions1188.2.2 Boxed Processor Heatsink Weight1258.2.3 Boxed Processor Retention Mechanism and Heatsink Supports1258.3 Thermal Specifications1258.3.1 Boxed Processor Cooling Requirements1258.3.2 Boxed Processor Contents1269 Debug Tools Specifications1279.1 Logic Analyzer Interface (LAI)1279.1.1 Mechanical Considerations1279.1.2 Electrical Considerations127文件大小: 3.1 MB页数: 128Language: English打开用户手册