数据表 (LF80565QH0566M)目录1 Introduction91.1 Terminology111.2 State of Data131.3 References132 Electrical Specifications152.1 Front Side Bus and GTLREF152.2 Decoupling Guidelines152.2.1 VCC Decoupling162.2.2 VTT Decoupling162.2.3 Front Side Bus AGTL+ Decoupling162.3 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking162.3.1 Front Side Bus Frequency Select Signals (BSEL[2:0])172.3.2 PLL Power Supply172.4 Voltage Identification (VID)172.5 Reserved, Unused, or Test Signals202.6 Front Side Bus Signal Groups202.7 CMOS Asynchronous and Open Drain Asynchronous Signals222.8 Test Access Port (TAP) Connection222.9 Mixing Processors232.10 Absolute Maximum and Minimum Ratings232.11 Processor DC Specifications242.11.1 Flexible Motherboard Guidelines (FMB)252.11.2 Platform Environmental Control Interface (PECI) DC Specifications352.11.3 VCC Overshoot Specification372.11.4 AGTL+ FSB Specifications382.12 Front Side Bus AC Specifications402.13 Processor AC Timing Waveforms453 Mechanical Specifications573.1 Package Mechanical Drawing573.2 Processor Component Keepout Zones603.3 Package Loading Specifications663.4 Package Handling Guidelines673.5 Package Insertion Specifications673.6 Processor Mass Specifications673.7 Processor Materials673.8 Processor Markings683.9 Processor Pin-Out Coordinates694 Pin Listing714.1 Pin Assignments714.1.1 Pin Listing by Pin Name714.1.2 Pin Listing by Pin Number795 Signal Definitions875.1 Signal Definitions.876 Thermal Specifications956.1 Package Thermal Specifications956.1.1 Thermal Specifications956.1.2 Thermal Metrology1026.2 Processor Thermal Features1036.2.1 Thermal Monitor Features1036.2.2 Thermal Monitor1036.2.3 Thermal Monitor 21046.2.4 On-Demand Mode1056.2.5 PROCHOT# Signal1066.2.6 FORCEPR# Signal1066.2.7 THERMTRIP# Signal1066.3 Platform Environment Control Interface (PECI)1076.3.1 Introduction1076.3.2 PECI Specifications1087 Features1117.1 Power-On Configuration Options1117.2 Clock Control and Low Power States1117.2.1 Normal State1127.2.2 HALT or Extended HALT State1127.2.3 Stop-Grant State1147.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State1157.3 Enhanced Intel SpeedStep® Technology1157.4 System Management Bus (SMBus) Interface1167.4.1 SMBus Device Addressing1177.4.2 PIROM and Scratch EEPROM Supported SMBus Transactions1187.4.3 Processor Information ROM (PIROM)1197.4.4 Checksums1377.4.5 Scratch EEPROM1378 Boxed Processor Specifications1398.1 Introduction1398.2 Thermal Specifications1398.2.1 Boxed Processor Cooling Requirements1399 Debug Tools Specifications1419.1 Debug Port System Requirements1419.2 Logic Analyzer Interface (LAI)1419.2.1 Mechanical Considerations1419.2.2 Electrical Considerations142文件大小: 4.4 MB页数: 142Language: English打开用户手册