用户手册 — Microchip Technology DV320032

目录

• 32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM) with Audio/Graphics/Touch (HMI), USB, and Advanced Analog

  1
• 1.0 Device Overview

  17
  • FIGURE 1-1: PIC32MX330/350/370/430/450/470 Block Diagram

    17
  • Table 1-1: Pinout I/O Descriptions

    18
• 2.0 Guidelines for Getting Started with 32-bit MCUs

  27
  • 2.1 Basic Connection Requirements

    27
  • 2.2 Decoupling Capacitors

    27
    • FIGURE 2-1: Recommended Minimum Connection

      28
  • 2.3 Capacitor on Internal Voltage Regulator (Vcap)

    28
  • 2.4 Master Clear (MCLR) Pin

    28
    • FIGURE 2-2: Example of MCLR Pin Connections

      28
  • 2.5 ICSP Pins

    29
  • 2.6 JTAG

    29
  • 2.7 Trace

    29
  • 2.8 External Oscillator Pins

    29
    • FIGURE 2-3: Suggested Oscillator Circuit Placement

      29
  • 2.9 Unused I/Os

    29
  • 2.10 Sosc Design Recommendation

    30
    • FIGURE 2-4: Recommended Oscillator Circuit Placement

      30
  • 2.11 Typical Application Connection Examples

    31
    • FIGURE 2-5: Capacitive Touch Sensing With Graphics Application

      31
    • FIGURE 2-6: Audio Playback Application

      31
    • FIGURE 2-7: Low-cost Controllerless (LCC) Graphics Application With Projected Capacitive Touch

      32
• 3.0 CPU

  33
  • 3.1 Features

    33
    • FIGURE 3-1: MIPS32® M4K® Processor Core Block Diagram

      33
  • 3.2 Architecture Overview

    34
    • Table 3-1: MIPS32® M4K® processor core High-Performance Integer Multiply/ Divide Unit Latencies and Repeat Rates

      34
    • Table 3-2: Coprocessor 0 Registers

      35
    • Table 3-3: MIPS32® M4K® processor core Exception Types

      36
  • 3.3 Power Management

    36
  • 3.4 EJTAG Debug Support

    36
• 4.0 Memory Organization

  37
  • 4.1 Memory Layout

    37
    • FIGURE 4-1: Memory Map for Devices with 64 KB of Program Memory

      38
    • FIGURE 4-2: Memory Map for Devices With 128 KB of Program Memory

      39
    • FIGURE 4-3: Memory Map for Devices With 256 KB of Program Memory

      40
    • FIGURE 4-4: Memory Map for Devices With 512 KB of Program Memory

      41
  • 4.2 Special Function Register Maps

    42
    • TABLE 4-1: Bus Matrix Register Map

      42
    • TABLE 4-2: Interrupt Register Map

      43
    • TABLE 4-3: Timer1 THROUGH Timer5 Register Map

      45
    • TABLE 4-4: Input Capture 1 THROUGH Input Capture 5 Register Map

      46
    • TABLE 4-5: Output Compare 1 THROUGH Output Compare 5 Register Map

      47
    • TABLE 4-6: I2C1 and I2C2 Register Map

      48
    • TABLE 4-7: UART1 THROUGH UART5 Register Map

      49
    • Table 4-8: spi2 and SPI2 Register Map

      51
    • TABLE 4-9: ADC Register Map

      52
    • TABLE 4-10: DMA Global Register Map

      54
    • TABLE 4-11: DMA CRC Register Map

      54
    • TABLE 4-12: DMA Channel 0 THROUGH Channel 3 Register Map

      55
    • TABLE 4-13: Comparator Register Map

      58
    • TABLE 4-14: Comparator Voltage Reference Register Map

      58
    • TABLE 4-15: Flash Controller Register Map

      59
    • TABLE 4-16: System Control Register Map

      60
    • TABLE 4-17: DEVCFG: Device Configuration Word Summary

      61
    • TABLE 4-18: Device and Revision ID Summary

      61
    • TABLE 4-19: PORTA Register Map for PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, PIC32MX370F512L, PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, and PIC32MX470F512L devices Only

      62
    • TABLE 4-20: PORTB Register Map

      63
    • TABLE 4-21: PORTC Register Map for PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, PIC32MX370F512l, PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, and PIC32MX470F512L Devices Only

      64
    • TABLE 4-22: PORTC Register Map for PIC32MX330F064H, PIC32MX350F128H, PIC32MX350F256H, PIC32MX370F512H, PIC32MX430F064H, PIC32MX450F128H, PIC32MX450F256H, and PIC32MX470F512H Devices Only

      65
    • TABLE 4-23: PORTD Register Map for PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, PIC32MX370F512L, PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, and PIC32MX470F512L Devices Only

      66
    • TABLE 4-24: PORTD Register Map for PIC32MX330F064H, PIC32MX350F128H, PIC32MX350F256H, PIC32MX370F512H, PIC32MX430F064H, PIC32MX450F128H, PIC32MX450F256H, PIC32MX470F512H Devices Only

      67
    • TABLE 4-25: PORTE Register Map for PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, PIC32MX370F512L, PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, PIC32MX470F512L Devices Only

      68
    • TABLE 4-26: PORTE Register Map for PIC32MX330F064H, PIC32MX350F128H, PIC32MX350F256H, PIC32MX370F512H, PIC32MX430F064H, PIC32MX450F128H, PIC32MX450F256H, and PIC32MX470F512H Devices Only

      69
    • TABLE 4-27: PORTF Register Map for PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, and PIC32MX370F512L Devices Only

      70
    • TABLE 4-28: PORTF Register Map for PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, and PIC32MX470F512L Devices Only

      71
    • TABLE 4-29: PORTF Register Map for PIC32MX330F064H, PIC32MX350F128H, PIC32MX350F256H, and PIC32MX370F512H Devices Only

      72
    • TABLE 4-30: PORTF Register Map for PIC32MX430F064H, PIC32MX450F128H, PIC32MX450F256H, and PIC32MX470F512H Devices Only

      73
    • TABLE 4-31: PORTG Register Map for PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, PIC32MX370F512L, PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, and PIC32MX470F512L Devices Only

      74
    • TABLE 4-32: PORTG Register Map for PIC32MX330F064H, PIC32MX350F128H, PIC32MX350F256H, PIC32MX370F512H, PIC32MX430F064H, PIC32MX450F128H, PIC32MX450F256H, and PIC32MX470F512H Devices Only

      75
    • Table 4-33: Peripheral Pin Select Input Register Map

      76
    • Table 4-34: Peripheral Pin Select Output Register Map

      78
    • TABLE 4-35: Parallel Master Port Register Map

      82
    • TABLE 4-36: Prefetch Register Map

      83
    • TABLE 4-37: RTCC Register Map

      84
    • TABLE 4-38: CTMU Register Map

      84
    • TABLE 4-39: USB Register Map

      85
  • 4.3 Control Registers

    88
    • Register 4-1: BMXCON: Bus Matrix Configuration Register

      88
    • Register 4-2: BMXDKPBA: Data RAM Kernel Program Base Address Register

      89
    • Register 4-3: BMXDUDBA: Data RAM User Data Base Address Register

      90
    • Register 4-4: BMXDUPBA: Data RAM User Program Base Address Register

      91
    • Register 4-5: BMXDRMSZ: Data RAM Size Register

      92
    • Register 4-6: BMXPUPBA: Program Flash (PFM) User Program Base Address Register

      92
    • Register 4-7: BMXPFMSZ: Program Flash (PFM) Size Register

      93
    • Register 4-8: BMXBOOTSZ: Boot Flash (IFM) Size Register

      93
• 5.0 Flash Program Memory

  95
  • 5.1 Control Registers

    96
    • Register 5-1: NVMCON: Programming Control Register

      96
    • Register 5-2: NVMKEY: Programming Unlock Register

      97
    • Register 5-3: NVMADDR: Flash Address Register

      97
    • Register 5-4: NVMDATA: Flash Program Data Register

      98
    • Register 5-5: NVMSRCADDR: Source Data Address Register

      98
• 6.0 Resets

  99
  • FIGURE 6-1: System Reset Block Diagram

    99
  • 6.1 Control Registers

    100
    • Register 6-1: RCON: Reset Control Register

      100
    • Register 6-2: RSWRST: Software Reset Register

      101
• 7.0 Interrupt Controller

  103
  • FIGURE 7-1: Interrupt Controller Module Block Diagram

    103
  • Table 7-1: Interrupt IRQ, Vector and Bit Location

    104
  • 7.1 Interrupts Control Registers

    106
    • Register 7-1: INTCON: Interrupt Control Register

      106
    • Register 7-2: INTSTAT: Interrupt Status Register

      107
    • Register 7-3: IPTMR: Interrupt Proximity Timer Register

      107
    • Register 7-4: IFSx: Interrupt Flag Status Register

      108
    • Register 7-5: IECx: Interrupt Enable Control Register

      108
    • Register 7-6: IPCx: Interrupt Priority Control Register

      109
• 8.0 Oscillator Configuration

  111
  • FIGURE 8-1: PIC32MX330/350/370/430/450/470 Family Clock Diagram

    112
  • 8.1 Control Registers

    113
    • Register 8-1: OSCCON: Oscillator Control Register

      113
    • Register 8-2: OSCTUN: FRC Tuning Register

      116
    • Register 8-3: REFOCON: Reference Oscillator Control Register

      117
    • Register 8-4: REFOTRIM: Reference Oscillator Trim Register

      119
• 9.0 Prefetch Cache

  121
  • 9.1 Features

    121
    • FIGURE 9-1: Prefetch Cache Module Block Diagram

      121
  • 9.2 Control Registers

    122
    • Register 9-1: CHECON: Cache Control Register

      122
    • Register 9-2: CHEACC: Cache Access Register

      123
    • Register 9-3: CHETAG: Cache TAG Register

      124
    • Register 9-4: CHEMSK: Cache TAG Mask Register

      125
    • Register 9-5: CHEW0: Cache Word 0

      125
    • Register 9-6: CHEW1: Cache Word 1

      126
    • Register 9-7: CHEW2: Cache Word 2

      126
    • Register 9-8: CHEW3: Cache Word 3

      127
    • Register 9-9: CHELRU: Cache LRU Register

      127
    • Register 9-10: CHEHIT: Cache Hit Statistics Register

      128
    • Register 9-11: CHEMIS: Cache Miss Statistics Register

      128
    • Register 9-12: CHEPFABT: Prefetch Cache Abort Statistics Register

      129
• 10.0 Direct Memory Access (DMA) Controller

  131
  • FIGURE 10-1: DMA Block Diagram

    131
  • 10.1 Control Registers

    132
    • Register 10-1: DMACON: DMA Controller Control Register

      132
    • Register 10-2: DMASTAT: DMA Status Register

      133
    • Register 10-3: DMAADDR: DMA Address Register

      133
    • Register 10-4: DCRCCON: DMA CRC Control Register

      134
    • Register 10-5: DCRCDATA: DMA CRC Data Register

      136
    • Register 10-6: DCRCXOR: DMA CRCXOR Enable Register

      136
    • Register 10-7: DCHxCON: DMA Channel ‘x’ Control Register

      137
    • Register 10-8: DCHxECON: DMA Channel ‘x’ Event Control Register

      138
    • Register 10-9: DCHxINT: DMA Channel ‘x’ Interrupt Control Register

      139
    • Register 10-10: DCHxSSA: DMA Channel ‘x’ Source Start Address Register

      141
    • Register 10-11: DCHxDSA: DMA Channel ‘x’ Destination Start Address Register

      141
    • Register 10-12: DCHxSSIZ: DMA Channel ‘x’ Source Size Register

      142
    • Register 10-13: DCHxDSIZ: DMA Channel ‘x’ Destination Size Register

      142
    • Register 10-14: DCHxSPTR: DMA Channel ‘x’ Source Pointer Register

      143
    • Register 10-15: DCHxDPTR: DMA Channel ‘x’ Destination Pointer Register

      143
    • Register 10-16: DCHxCSIZ: DMA Channel ‘x’ Cell-Size Register

      144
    • Register 10-17: DCHxCPTR: DMA Channel ‘x’ Cell Pointer Register

      144
    • Register 10-18: DCHxDAT: DMA Channel ‘x’ Pattern Data Register

      145
• 11.0 USB On-The-Go (OTG)

  147
  • FIGURE 11-1: PIC32MX430/450/470 USB Interface Diagram

    148
  • 11.1 Control Registers

    149
    • Register 11-1: U1OTGIR: USB OTG Interrupt Status Register

      149
    • Register 11-2: U1OTGIE: USB OTG Interrupt Enable Register

      150
    • Register 11-3: U1OTGSTAT: USB OTG Status Register

      151
    • Register 11-4: U1OTGCON: USB OTG Control Register

      152
    • Register 11-5: U1PWRC: USB Power Control Register

      153
    • Register 11-6: U1IR: USB Interrupt Register

      154
    • Register 11-7: U1IE: USB Interrupt Enable Register

      155
    • Register 11-8: U1EIR: USB Error Interrupt Status Register

      156
    • Register 11-9: U1EIE: USB Error Interrupt Enable Register

      158
    • Register 11-10: U1STAT: USB Status Register

      159
    • Register 11-11: U1CON: USB Control Register

      160
    • Register 11-12: U1ADDR: USB Address Register

      162
    • Register 11-13: U1FRML: USB Frame Number Low Register

      162
    • Register 11-14: U1FRMH: USB Frame Number High Register

      163
    • Register 11-15: U1TOK: USB Token Register

      163
    • Register 11-16: U1SOF: USB SOF Threshold Register

      164
    • Register 11-17: U1BDTP1: USB BDT Page 1 Register

      164
    • Register 11-18: U1BDTP2: USB BDT PAGE 2 Register

      165
    • Register 11-19: U1BDTP3: USB BDT PAGE 3 Register

      165
    • Register 11-20: U1CNFG1: USB Configuration 1 Register

      166
    • Register 11-21: U1EP0-U1EP15: USB Endpoint Control Register

      167
• 12.0 I/O Ports

  169
  • FIGURE 12-1: Block Diagram of a Typical Multiplexed Port Structure

    169
  • 12.1 Parallel I/O (PIO) Ports

    170
  • 12.2 CLR, SET, and INV Registers

    170
  • 12.3 Peripheral Pin Select

    171
    • FIGURE 12-2: Remappable Input Example for U1RX

      171
    • TABLE 12-1: Input Pin Selection

      172
    • FIGURE 12-3: Example of Multiplexing of Remappable Output for RPA0

      174
    • Table 12-2: Output Pin Selection

      175
  • 12.4 Control Registers

    177
    • Register 12-1: [pin name]R: Peripheral Pin Select Input Register

      177
    • Register 12-2: RPnR: Peripheral Pin Select Output Register

      177
    • Register 12-3: CNCONx: Change Notice control for PORTx Register (x = A – G)

      178
• 13.0 Timer1

  179
  • 13.1 Additional Supported Features

    179
    • FIGURE 13-1: Timer1 Block Diagram

      179
  • 13.2 Control Register

    180
    • Register 13-1: T1CON: Type A Timer Control Register

      180
• 14.0 Timer2/3, Timer4/5

  183
  • 14.1 Additional Supported Features

    183
    • FIGURE 14-1: Timer2, 3, 4, 5 Block Diagram (16-bit)

      183
    • FIGURE 14-2: Timer2/3, 4/5 Block Diagram (32-bit)(1)

      184
  • 14.2 Control Register

    185
    • Register 14-1: TxCON: Type B Timer Control Register

      185
• 15.0 Input Capture

  187
  • FIGURE 15-1: Input Capture Block Diagram

    187
  • 15.1 Control Register

    188
    • Register 15-1: ICxCON: Input Capture ‘x’ Control Register

      188
• 16.0 Output Compare

  191
  • FIGURE 16-1: Output Compare Module Block Diagram

    191
  • 16.1 Control Register

    192
    • Register 16-1: OCxCON: Output Compare ‘x’ Control Register

      192
• 17.0 Serial Peripheral Interface (SPI)

  193
  • FIGURE 17-1: SPI Module Block Diagram

    193
  • 17.1 Control Registers

    194
    • Register 17-1: SPIx CON: SPI Control Register

      194
    • Register 17-2: SPIxCON2: SPI Control Register 2

      197
    • Register 17-3: SPIxSTAT: SPI Status Register

      198
• 18.0 Inter-Integrated Circuit™ (I2C™)

  201
  • FIGURE 18-1: I2C™ Block Diagram

    202
  • 18.1 Control Registers

    203
    • Register 18-1: I2CxCON: I2C™ Control Register

      203
    • Register 18-2: I2CxSTAT: I2C™ Status Register

      205
• 19.0 Universal Asynchronous Receiver Transmitter (UART)

  207
  • FIGURE 19-1: UART Simplified Block Diagram

    207
  • 19.1 Control Registers

    208
    • Register 19-1: UxMODE: UARTx Mode Register

      208
    • Register 19-2: UxSTA: UARTx Status and Control Register

      210
  • 19.2 Timing Diagrams

    212
    • FIGURE 19-2: UART Reception

      212
    • FIGURE 19-3: Transmission (8-bit or 9-bit Data)

      212
• 20.0 Parallel Master Port (PMP)

  213
  • FIGURE 20-1: PMP Module Pinout and Connections to External Devices

    213
  • 20.1 Control Registers

    214
    • Register 20-1: PMCON: Parallel Port Control Register

      214
    • Register 20-2: PMMODE: Parallel Port Mode Register

      216
    • Register 20-3: PMADDR: Parallel Port Address Register

      218
    • Register 20-4: PMAEN: Parallel Port Pin Enable Register

      219
    • Register 20-5: PMSTAT: Parallel Port Status Register (Slave modes only)

      220
• 21.0 Real-Time Clock and Calendar (RTCC)

  221
  • FIGURE 21-1: RTCC Block Diagram

    221
  • 21.1 Control Registers

    222
    • Register 21-1: RTCCON: RTC Control Register

      222
    • Register 21-2: RTCALRM: RTC ALARM Control Register

      224
    • Register 21-3: RTCTIME: RTC Time Value Register

      226
    • Register 21-4: RTCDATE: RTC Date Value Register

      227
    • Register 21-5: ALRMTIME: Alarm Time Value Register

      228
    • Register 21-6: ALRMDATE: Alarm Date Value Register

      229
• 22.0 10-bit Analog-to-Digital Converter (ADC)

  231
  • FIGURE 22-1: ADC1 Module Block Diagram

    231
  • FIGURE 22-2: ADC Conversion Clock Period Block Diagram

    232
  • 22.1 Control Registers

    233
    • Register 22-1: AD1CON1: ADC Control Register 1

      233
    • Register 22-2: AD1CON2: ADC Control Register 2

      235
    • Register 22-3: AD1CON3: ADC Control Register 3

      236
    • Register 22-4: AD1CHS: ADC Input Select Register

      237
    • Register 22-5: AD1CSSL: ADC Input Scan Select Register

      238
• 23.0 Comparator

  239
  • FIGURE 23-1: Comparator Block Diagram

    239
  • 23.1 Control Registers

    240
    • Register 23-1: CMxCON: Comparator Control Register

      240
    • Register 23-2: CMSTAT: Comparator Status Register

      241
• 24.0 Comparator Voltage Reference (CVref)

  243
  • FIGURE 24-1: Comparator Voltage Reference Block Diagram

    243
  • 24.1 Control Register

    244
    • Register 24-1: CVRCON: Comparator Voltage Reference Control Register

      244
• 25.0 Charge Time Measurement Unit (CTMU)

  245
  • FIGURE 25-1: CTMU Block Diagram

    245
  • 25.1 Control Register

    246
    • Register 25-1: CTMUCON: CTMU Control Register

      246
• 26.0 Power-Saving Features

  249
  • 26.1 Power Saving with CPU Running

    249
  • 26.2 CPU Halted Methods

    249
  • 26.3 Power-Saving Operation

    249
  • 26.4 Peripheral Module Disable

    251
    • Table 26-1: Peripheral Module Disable Bits and Locations

      251
• 27.0 Special Features

  253
  • 27.1 Configuration Bits

    253
    • Register 27-1: DEVCFG0: Device Configuration Word 0

      253
    • Register 27-2: DEVCFG1: Device Configuration Word 1

      255
    • Register 27-3: DEVCFG2: Device Configuration Word 2

      257
    • Register 27-4: DEVCFG3: Device Configuration Word 3

      259
    • Register 27-5: CFGCON: Configuration Control Register

      260
    • Register 27-6: DEVID: Device and Revision ID Register

      261
  • 27.2 Watchdog Timer (WDT)

    262
    • Figure 27-1: Watchdog and Power-Up Timer Block Diagram

      262
    • Register 27-7: WDTCON: Watchdog Timer Control Register

      263
  • 27.3 On-Chip Voltage Regulator

    264
    • Figure 27-2: Connections for the On-Chip Regulator

      264
  • 27.4 Programming and Diagnostics

    264
    • Figure 27-3: Block Diagram of Programming, Debugging and Trace Ports

      264
• 28.0 Instruction Set

  265
• 29.0 Development Support

  267
  • 29.1 MPLAB X Integrated Development Environment Software

    267
  • 29.2 MPLAB XC Compilers

    268
  • 29.3 MPASM Assembler

    268
  • 29.4 MPLINK Object Linker/ MPLIB Object Librarian

    268
  • 29.5 MPLAB Assembler, Linker and Librarian for Various Device Families

    268
  • 29.6 MPLAB X SIM Software Simulator

    269
  • 29.7 MPLAB REAL ICE In-Circuit Emulator System

    269
  • 29.8 MPLAB ICD 3 In-Circuit Debugger System

    269
  • 29.9 PICkit 3 In-Circuit Debugger/ Programmer

    269
  • 29.10 MPLAB PM3 Device Programmer

    269
  • 29.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits

    270
  • 29.12 Third-Party Development Tools

    270
• 30.0 Electrical Characteristics

  271
  • 30.1 DC Characteristics

    272
    • Table 30-1: Operating MIPS vs. Voltage

      272
    • Table 30-2: Thermal Operating Conditions

      272
    • Table 30-3: Thermal Packaging Characteristics

      272
    • Table 30-4: DC Temperature and Voltage Specifications

      273
    • Table 30-5: DC Characteristics: Operating Current (Idd)

      274
    • Table 30-6: DC Characteristics: Idle Current (Iidle)

      275
    • Table 30-7: DC Characteristics: Power-Down Current (Ipd)

      276
    • Table 30-8: DC Characteristics: I/O Pin Input Specifications

      277
    • TABLE 30-9: DC Characteristics: I/O Pin Output Specifications

      280
    • Table 30-10: Electrical Characteristics: BOR

      281
    • Table 30-11: Electrical Characteristics: HVD

      281
    • Table 30-12: DC Characteristics: Program Memory

      282
    • Table 30-13: DC Characteristics: Program Flash Memory Wait State

      282
    • Table 30-14: Comparator Specifications

      283
    • Table 30-15: Internal Voltage Regulator Specifications

      283
  • 30.2 AC Characteristics and Timing Parameters

    284
    • Figure 30-1: Load Conditions for Device Timing Specifications

      284
    • Table 30-16: Capacitive Loading Requirements on Output Pins

      284
    • Figure 30-2: External Clock Timing

      284
    • Table 30-17: External Clock Timing Requirements

      285
    • Table 30-18: PLL Clock Timing Specifications

      286
    • Table 30-19: Internal FRC Accuracy

      286
    • Table 30-20: Internal LPRC Accuracy

      286
    • Figure 30-3: I/O Timing Characteristics

      287
    • Table 30-21: I/O Timing Requirements

      287
    • Figure 30-4: Power-On Reset Timing Characteristics

      288
    • Figure 30-5: External Reset Timing Characteristics

      289
    • Table 30-22: Resets Timing

      289
    • Figure 30-6: Timer1, 2, 3, 4, 5 External Clock Timing Characteristics

      290
    • Table 30-23: Timer1 External Clock Timing Requirements(1)

      290
    • Table 30-24: Timer2, 3, 4, 5 External Clock Timing Requirements

      291
    • Figure 30-7: Input Capture (CAPx) Timing Characteristics

      291
    • Table 30-25: Input Capture Module Timing Requirements

      291
    • Figure 30-8: Output Compare Module (OCx) Timing Characteristics

      292
    • Table 30-26: Output Compare Module Timing Requirements

      292
    • Figure 30-9: OCx/PWM Module Timing Characteristics

      292
    • Table 30-27: Simple OCx/PWM Mode Timing Requirements

      292
    • Figure 30-10: SPIx Module Master Mode (CKE = 0) Timing Characteristics

      293
    • Table 30-28: SPIx Master Mode (CKE = 0) Timing Requirements

      293
    • Figure 30-11: SPIx Module Master Mode (CKE = 1) Timing Characteristics

      294
    • Table 30-29: SPIx Module Master Mode (CKE = 1) Timing Requirements

      294
    • Figure 30-12: SPIx Module Slave Mode (CKE = 0) Timing Characteristics

      295
    • Table 30-30: SPIx Module Slave Mode (CKE = 0) Timing Requirements

      295
    • Figure 30-13: SPIx Module Slave Mode (CKE = 1) Timing Characteristics

      296
    • Table 30-31: SPIx Module Slave Mode (CKE = 1) Timing Requirements

      296
    • Figure 30-14: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)

      298
    • Figure 30-15: I2Cx Bus Data Timing Characteristics (Master Mode)

      298
    • Table 30-32: I2Cx Bus Data Timing Requirements (Master Mode)

      299
    • Figure 30-16: I2Cx Bus Start/Stop Bits Timing Characteristics (Slave Mode)

      301
    • Figure 30-17: I2Cx Bus Data Timing Characteristics (Slave Mode)

      301
    • Table 30-33: I2Cx Bus Data Timing Requirements (Slave Mode)

      302
    • Table 30-34: ADC Module Specifications

      304
    • Table 30-35: 10-bit Conversion Rate Parameters

      306
    • Table 30-36: Analog-to-Digital Conversion Timing Requirements

      307
    • Figure 30-18: Analog-to-Digital Conversion (10-bit Mode) Timing Characteristics (ASAM = 0, SSRC<2:0> = 000)

      308
    • Figure 30-19: Analog-to-Digital Conversion (10-bit mode) Timing Characteristics (ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)

      309
    • Figure 30-20: Parallel Slave Port Timing

      310
    • Table 30-37: Parallel Slave Port Requirements

      310
    • Figure 30-21: Parallel Master Port Read Timing Diagram

      311
    • Table 30-38: Parallel Master Port Read Timing Requirements

      311
    • Figure 30-22: Parallel Master Port Write Timing Diagram

      312
    • Table 30-39: Parallel Master Port Write Timing Requirements

      312
    • Table 30-40: OTG Electrical Specifications

      313
    • TABLE 30-41: CTMU Current Source Specifications

      314
    • Figure 30-23: EJTAG Timing Characteristics

      315
    • Table 30-42: EJTAG Timing Requirements

      315
• 31.0 DC and AC Device Characteristics Graphs

  317
  • FIGURE 31-1: Voh – 4x Driver Pins

    317
  • FIGURE 31-2: Voh – 8x Driver Pins

    317
  • FIGURE 31-3: Vol – 4x Driver Pins

    317
  • FIGURE 31-4: Vol – 8x Driver Pins

    317
  • FIGURE 31-5: Typical Ipd Current @ Vdd = 3.3V

    318
  • FIGURE 31-6: Typical Ipd Current @ Vdd = 3.3V

    318
  • FIGURE 31-7: Typical Ipd Current @ Vdd = 3.3V

    318
  • FIGURE 31-8: Typical Iidle Current @ Vdd = 3.3V

    318
  • FIGURE 31-9: Typical Iidle Current @ Vdd = 3.3V

    319
  • FIGURE 31-10: Typical Iidle Current @ Vdd = 3.3V

    319
  • FIGURE 31-11: Typical Idd Current @ Vdd = 3.3V

    319
  • FIGURE 31-12: Typical Idd Current @ Vdd = 3.3V

    319
  • FIGURE 31-13: Typical Idd Current @ Vdd = 3.3V

    320
  • FIGURE 31-14: Typical FRC Frequency @ Vdd = 3.3V

    320
  • FIGURE 31-15: Typical LPRC Frequency @ Vdd = 3.3V

    320
  • FIGURE 31-16: Typical CTMU Temperature DIODE Forward Voltage

    320
• 32.0 Packaging Information

  321
  • 32.1 Package Marking Information

    321
  • 32.1 Package Marking Information (Continued)

    322
  • 32.2 Package Details

    323
• Appendix A: Revision History

  335
  • TABLE A-1: Major Section Updates

    335
  • TABLE A-2: Major Section Updates

    336
• INDEX

  337
• The Microchip Web Site

  341
• Customer Change Notification Service

  341
• Customer Support

  341
• Worldwide Sales and Service

  344