用户手册 — Microchip Technology IC MCU FLASH PIC16F874-20I/P DIP-40 MCP

目录

• Devices Included in this Data Sheet:

  1
• Microcontroller Core Features:

  1
• Pin Diagram

  1
• Peripheral Features:

  1
• Pin Diagrams

  2
• Table of Contents

  4
  • 1.0 Device Overview 5

    4
  • 2.0 Memory Organization 11

    4
  • 3.0 I/O Ports 29

    4
  • 4.0 Data EEPROM and FLASH Program Memory 41

    4
  • 5.0 Timer0 Module 47

    4
  • 6.0 Timer1 Module 51

    4
  • 7.0 Timer2 Module 55

    4
  • 8.0 Capture/Compare/PWM Modules 57

    4
  • 9.0 Master Synchronous Serial Port (MSSP) Module 65

    4
  • 10.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) 95

    4
  • 11.0 Analog-to-Digital Converter (A/D) Module 111

    4
  • 12.0 Special Features of the CPU 119

    4
  • 13.0 Instruction Set Summary 135

    4
  • 14.0 Development Support 143

    4
  • 15.0 Electrical Characteristics 149

    4
  • 16.0 DC and AC Characteristics Graphs and Tables 177

    4
  • 17.0 Packaging Information 189

    4
    • Appendix A: Revision History 197

      4
    • Appendix B: Device Differences 197

      4
    • Appendix C: Conversion Considerations 198

      4
      • TO OUR VALUED CUSTOMERS

        4
• Most Current Data Sheet

  4
• Errata

  4
• Customer Notification System

  4
• 1.0 Device Overview

  5
• 2.0 Memory Organization

  11
  • 2.1 Program Memory Organization

    11
  • 2.2 Data Memory Organization

    12
    • 2.2.1 General purpose Register File

      12
    • 2.2.2 Special Function Registers

      15
      • 2.2.2.1 STATUS Register

        18
      • 2.2.2.2 OPTION_REG Register

        19
      • 2.2.2.3 INTCON Register

        20
      • 2.2.2.4 PIE1 Register

        21
      • 2.2.2.5 PIR1 Register

        22
      • 2.2.2.6 PIE2 Register

        23
      • 2.2.2.7 PIR2 Register

        24
      • 2.2.2.8 PCON Register

        25
  • 2.3 PCL and PCLATH

    26
    • 2.3.1 computed GOTO

      26
    • 2.3.2 Stack

      26
  • 2.4 Program Memory Paging

    26
  • 2.5 Indirect Addressing, INDF and FSR Registers

    27
• 3.0 I/O Ports

  29
  • 3.1 PORTA and the TRISA Register

    29
  • 3.2 PORTB and the TRISB Register

    31
  • 3.3 PORTC and the TRISC Register

    33
  • 3.4 PORTD and TRISD Registers

    35
  • 3.5 PORTE and TRISE Register

    36
  • 3.6 Parallel Slave Port

    38
• 4.0 Data EEPROM and Flash Program Memory

  41
  • 4.1 EECON1 and EECON2 Registers

    41
  • 4.2 Reading the EEPROM Data Memory

    43
  • 4.3 Writing to the EEPROM Data Memory

    43
  • 4.4 Reading the FLASH Program Memory

    44
  • 4.5 Writing to the FLASH Program Memory

    44
  • 4.6 Write Verify

    45
  • 4.7 Protection Against Spurious Writes

    45
  • 4.8 Operation While Code Protected

    45
  • 4.9 FLASH Program Memory Write Protection

    46
• 5.0 Timer0 Module

  47
  • 5.1 Timer0 Interrupt

    47
  • 5.2 Using Timer0 with an External Clock

    48
  • 5.3 Prescaler

    48
• 6.0 Timer1 Module

  51
  • 6.1 Timer1 Operation in Timer Mode

    52
  • 6.2 Timer1 Counter Operation

    52
  • 6.3 Timer1 Operation in Synchronized Counter Mode

    52
  • 6.4 Timer1 Operation in Asynchronous Counter Mode

    53
    • 6.4.1 Reading and writing Timer1 in asynchronous counter mode

      53
  • 6.5 Timer1 Oscillator

    53
  • 6.6 Resetting Timer1 using a CCP Trigger Output

    53
  • 6.7 Resetting of Timer1 Register Pair (TMR1H, TMR1L)

    54
  • 6.8 Timer1 Prescaler

    54
• 7.0 Timer2 Module

  55
  • 7.1 Timer2 Prescaler and Postscaler

    56
  • 7.2 Output of TMR2

    56
• 8.0 Capture/Compare/PWM Modules

  57
  • 8.1 Capture Mode

    59
    • 8.1.1 CCP pin Configuration

      59
    • 8.1.2 Timer1 Mode Selection

      59
    • 8.1.3 Software Interrupt

      59
    • 8.1.4 CCP Prescaler

      59
  • 8.2 Compare Mode

    60
    • 8.2.1 CCP Pin Configuration

      60
    • 8.2.2 timer1 Mode Selection

      60
    • 8.2.3 Software Interrupt Mode

      60
    • 8.2.4 Special Event Trigger

      60
  • 8.3 PWM Mode (PWM)

    61
    • 8.3.1 PWM period

      61
    • 8.3.2 PWM Duty Cycle

      61
    • 8.3.3 SetUp for PWM Operation

      62
• 9.0 Master Synchronous Serial Port (MSSP) Module

  65
  • 9.1 SPI Mode

    69
    • 9.1.1 Master Mode

      70
    • 9.1.2 Slave Mode

      71
  • 9.2 MSSP I2C Operation

    73
    • 9.2.1 SLAVE Mode

      74
      • 9.2.1.1 Addressing

        74
      • 9.2.1.2 Slave Reception

        74
      • 9.2.1.3 Slave Transmission

        75
    • 9.2.2 General Call Address Support

      76
    • 9.2.3 Sleep Operation

      77
    • 9.2.4 Effects of a Reset

      77
    • 9.2.5 Master Mode

      78
    • 9.2.6 Multi-master Mode

      78
    • 9.2.7 I2C Master Mode Support

      79
      • 9.2.7.1 I2C Master Mode Operation

        79
    • 9.2.8 Baud Rate Generator

      79
    • 9.2.9 I2C Master Mode Start Condition Timing

      80
      • 9.2.9.1 WCOL Status Flag

        80
    • 9.2.10 I2C Master Mode Repeated Start Condition Timing

      81
      • 9.2.10.1 WCOL Status Flag

        81
    • 9.2.11 I2C Master Mode Transmission

      82
      • 9.2.11.1 BF Status Flag

        82
      • 9.2.11.2 WCOL Status Flag

        82
      • 9.2.11.3 ACKSTAT Status Flag

        82
    • 9.2.12 I2C Master Mode Reception

      84
      • 9.2.12.1 BF Status Flag

        84
      • 9.2.12.2 SSPOV Status Flag

        84
      • 9.2.12.3 WCOL Status Flag

        84
    • 9.2.13 Acknowledge Sequence Timing

      86
      • 9.2.13.1 WCOL Status Flag

        86
    • 9.2.14 Stop Condition Timing

      87
      • 9.2.14.1 WCOL Status Flag

        87
    • 9.2.15 Clock Arbitration

      88
    • 9.2.16 Sleep Operation

      88
    • 9.2.17 Effects of a Reset

      88
    • 9.2.18 Multi -Master Communication, Bus Collision, And Bus Arbitration

      89
      • 9.2.18.1 Bus Collision During a START Condition

        90
      • 9.2.18.2 Bus Collision During a Repeated START Condition

        92
      • 9.2.18.3 Bus Collision During a STOP Condition

        93
  • 9.3 Connection Considerations for I2C Bus

    94
• 10.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)

  95
  • 10.1 USART Baud Rate Generator (BRG)

    97
    • 10.1.1 SAMPLING

      97
  • 10.2 USART Asynchronous Mode

    99
    • 10.2.1 USART Asynchronous Transmitter

      99
    • 10.2.2 USART Asynchronous Receiver

      101
    • 10.2.3 Setting up 9-bit mode with Address Detect

      103
  • 10.3 USART Synchronous Master Mode

    105
    • 10.3.1 USART Synchronous Master Transmission

      105
    • 10.3.2 USART Synchronous Master Reception

      107
  • 10.4 USART Synchronous Slave Mode

    108
    • 10.4.1 USART Synchronous Slave Transmit

      108
    • 10.4.2 USART Synchronous Slave Reception

      109
• 11.0 Analog-to-Digital Converter (A/D) Module

  111
  • 11.1 A/D Acquisition Requirements

    114
  • 11.2 Selecting the A/D Conversion Clock

    115
  • 11.3 Configuring Analog Port Pins

    115
  • 11.4 A/D Conversions

    116
    • 11.4.1 A/D Result Registers

      116
  • 11.5 A/D Operation During SLEEP

    117
  • 11.6 Effects of a RESET

    117
• 12.0 Special Features of the CPU

  119
  • 12.1 Configuration Bits

    119
  • 12.2 Oscillator Configurations

    121
    • 12.2.1 Oscillator Types

      121
    • 12.2.2 Crystal Oscillator/CERAmic Resonators

      121
    • 12.2.3 RC Oscillator

      122
  • 12.3 RESET

    123
  • 12.4 Power-On Reset (POR)

    124
  • 12.5 Power-up Timer (PWRT)

    124
  • 12.6 Oscillator Start-up Timer (OST)

    124
  • 12.7 Brown-out Reset (BOR)

    124
  • 12.8 Time-out Sequence

    124
  • 12.9 Power Control/Status Register (PCON)

    124
  • 12.10 Interrupts

    129
    • 12.10.1 INT Interrupt

      130
    • 12.10.2 TMR0 Interrupt

      130
    • 12.10.3 PortB INTCON CHANGE

      130
  • 12.11 Context Saving During Interrupts

    130
  • 12.12 Watchdog Timer (WDT)

    131
  • 12.13 Power-down Mode (SLEEP)

    132
    • 12.13.1 Wake-up from SLEEP

      132
    • 12.13.2 Wake-Up Using Interrupts

      132
  • 12.14 In-Circuit Debugger

    133
  • 12.15 Program Verification/Code Protection

    133
  • 12.16 ID Locations

    133
  • 12.17 In-Circuit Serial Programming

    134
  • 12.18 Low Voltage ICSP Programming

    134
• 13.0 Instruction Set Summary

  135
  • 13.1 Instruction Descriptions

    137
• 14.0 Development Support

  143
  • 14.1 MPLAB Integrated Development Environment Software

    143
  • 14.2 MPASM Assembler

    143
  • 14.3 MPLAB C17 and MPLAB C18 C Compilers

    143
  • 14.4 MPLINK Object Linker/ MPLIB Object Librarian

    144
  • 14.5 MPLAB SIM Software Simulator

    144
  • 14.6 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE

    144
  • 14.7 ICEPIC In-Circuit Emulator

    144
  • 14.8 MPLAB ICD In-Circuit Debugger

    145
  • 14.9 PRO MATE II Universal Device Programmer

    145
  • 14.10 PICSTART Plus Entry Level Development Programmer

    145
  • 14.11 PICDEM 1 Low Cost PIC MCU Demonstration Board

    145
  • 14.12 PICDEM 2 Low Cost PIC16CXX Demonstration Board

    145
  • 14.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board

    146
  • 14.14 PICDEM 17 Demonstration Board

    146
  • 14.15 KeeLoq Evaluation and Programming Tools

    146
• 15.0 Electrical Characteristics

  149
  • 15.1 DC Characteristics: PIC16F873/874/876/877-04 (Commercial, Industrial) PIC16F873/874/876/877-20 (Commercial, Industrial) PIC16LF873/874/876/877-04 (Commercial, Industrial)

    152
    • D001

      152
    • D001A

      152
    • D002

      152
    • D003

      152
    • D004

      152
    • D005

      152
    • D023

      154
      • Legend: Rows with standard voltage device data only are shaded for improved readability.

        152
      • † Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only, and are not tested.

        152
  • 15.2 DC Characteristics: PIC16F873/874/876/877-04 (Commercial, Industrial) PIC16F873/874/876/877-20 (Commercial, Industrial) PIC16LF873/874/876/877-04 (Commercial, Industrial)

    155
  • 15.3 DC Characteristics: PIC16F873/874/876/877-04 (Extended) PIC16F873/ 874/ 876/ 877-10 (Extended)

    157
    • D001

      157
    • D001A

      157
    • D001A

      157
    • D002

      157
    • D003

      157
    • D004

      157
    • D005

      157
    • D023

      158
      • † Data is “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only, and are not tested.

        157
  • 15.4 DC Characteristics: PIC16F873/874/876/877-04 (Extended) PIC16F873/874/876/877-10 (Extended)

    159
  • 15.5 Timing Parameter Symbology

    161
• 16.0 DC and AC Characteristics Graphs and Tables

  177
• 17.0 Packaging Information

  189
  • 17.1 Package Marking Information

    189
  • Package Marking Information (Cont’d)

    190
  • 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)

    191
  • 28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)

    192
  • 40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)

    193
  • 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

    194
  • 44-Lead Plastic Metric Quad Flatpack (PQ) 10x10x2 mm Body, 1.6/0.15 mm Lead Form (MQFP)

    195
  • 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)

    196
• Appendix A: Revision History

  197
• Appendix B: Device Differences

  197
• Appendix C: Conversion CONSIDERATIONS

  198
• Index

  199
  • A

    199
  • Acquisition Requirements 114

    199
  • ADCON0 Register 111

    199
  • ADCON1 Register 112

    199
  • ADIF bit 112

    199
  • Analog Input Model Block Diagram 114

    199
  • Analog Port Pins 7, 8, 9, 36, 38

    199
  • Associated Registers and Bits 117

    199
  • Block Diagram 113

    199
  • Calculating Acquisition Time 114

    199
  • Configuring Analog Port Pins 115

    199
  • Configuring the Interrupt 113

    199
  • Configuring the Module 113

    199
  • Conversion Clock 115

    199
  • Conversions 116

    199
  • Delays 114

    199
  • Effects of a RESET 117

    199
  • GO/DONE bit 112

    199
  • Internal Sampling Switch (Rss) Impedence 114

    199
  • Operation During SLEEP 117

    199
  • Result Registers 116

    199
  • Sampling Requirements 114

    199
  • Source Impedence 114

    199
  • Time Delays 114

    199
  • AN552 (Implementing Wake-up on Key Strokes Using PIC16CXXX) 31

    199
  • AN556 (Implementing a Table Read) 26

    199
  • AN578 (Use of the SSP Module in the I2C Multi-Master Environment) 73

    199
  • PIC16F873/PIC16F876 Block Diagram 5

    199
  • PIC16F874/PIC16F877 Block Diagram 6

    199
  • MPASM Assembler 143

    199
    • B

      199
  • A/D 113

    199
  • A/D Converter 113

    199
  • Analog Input Model 114

    199
  • Baud Rate Generator 79

    199
  • Capture Mode 59

    199
  • Compare Mode 60

    199
  • I2C Master Mode 78

    199
  • I2C Module 73

    199
  • I2C Slave Mode 73

    199
  • Interrupt Logic 129

    199
  • PIC16F873/PIC16F876 5

    199
  • PIC16F874/PIC16F877 6

    199
  • PORTA

    199
  • PORTB

    199
  • PORTC

    199
  • PORTD 35

    199
  • PORTD and PORTE (Parallel Slave Port) 38

    199
  • PORTE 36

    199
  • PWM Mode 61

    199
  • RESET Circuit 123

    199
  • SSP (I2C Mode) 73

    199
  • SSP (SPI Mode) 69

    199
  • Timer0/WDT Prescaler 47

    199
  • Timer1 52

    199
  • Timer2 55

    199
  • USART Asynchronous Receive 101

    199
  • USART Asynchronous Receive (9-bit Mode) 103

    199
  • USART Transmit 99

    199
  • Watchdog Timer 131

    199
  • BOR Status (BOR Bit) 25

    199
    • C

      199
  • Associated Registers

    199
  • Capture Mode 59

    199
  • CCP Timer Resources 57

    199
  • CCP1

    199
  • CCP2

    199
  • Compare

    199
  • Compare Mode 60

    199
  • Interaction of Two CCP Modules (table) 57

    199
  • PWM Mode 61

    200
  • Special Event Trigger and A/D Conversions 60

    200
  • Call of a Subroutine in Page 1 from Page 0 26

    200
  • EEPROM Data Read 43

    200
  • EEPROM Data Write 43

    200
  • FLASH Program Read 44

    200
  • FLASH Program Write 45

    200
  • Indirect Addressing 27

    200
  • Initializing PORTA 29

    200
  • Saving STATUS, W and PCLATH Registers 130

    200
  • Data EEPROM and FLASH Program Memory 45

    200
    • D

      200
  • Associated Registers 46

    200
  • Code Protection 45

    200
  • Reading 43

    200
  • Special Functions Registers 41

    200
  • Spurious Write Protection 45

    200
  • Write Verify 45

    200
  • Writing to 43

    200
  • Bank Select (RP1:RP0 Bits) 12, 18

    200
  • General Purpose Registers 12

    200
  • Register File Map 13, 14

    200
  • Special Function Registers 15

    200
  • Commercial and Industrial 152– 156

    200
  • Extended 157– 160

    200
    • E

      200
    • F

      200
  • Associated Registers 46

    200
  • Code Protection 45

    200
  • Configuration Bits and Read/Write State 46

    200
  • Reading 44

    200
  • Special Function Registers 41

    200
  • Spurious Write Protection 45

    200
  • Write Protection 46

    200
  • Write Verify 45

    200
  • Writing to 44

    200
    • G

      200
    • I

      200
  • Connection Considerations 94

    200
  • Sample Device Configuration 94

    200
  • Acknowledge Sequence Timing 86

    200
  • Addressing 74

    200
  • Associated Registers 77

    200
  • Baud Rate Generator 79

    200
  • Block Diagram 78

    200
  • BRG Block Diagram 79

    200
  • BRG Reset due to SDA Collision 91

    200
  • BRG Timing 80

    200
  • Bus Arbitration 89

    200
  • Bus Collision 89

    200
  • Bus Collision Timing 89

    200
  • Clock Arbitration 88

    200
  • Clock Arbitration Timing (Master Transmit) 88

    200
  • Conditions to not give ACK Pulse 74

    200
  • General Call Address Support 76

    200
  • Master Mode 78

    200
  • Master Mode 7-bit Reception Timing 85

    200
  • Master Mode Block Diagram 78

    200
  • Master Mode Operation 79

    201
  • Master Mode START Condition 80

    201
  • Master Mode Transmission 82

    201
  • Master Mode Transmit Sequence 79

    201
  • Multi-Master Communication 89

    201
  • Multi-master Mode 78

    201
  • Operation 73

    201
  • Repeat START Condition Timing 81

    201
  • Slave Mode 74

    201
  • Slave Reception 74

    201
  • Slave Transmission 75

    201
  • SSPBUF 73

    201
  • STOP Condition Receive or Transmit Timing 87

    201
  • STOP Condition Timing 87

    201
  • Waveforms for 7-bit Reception 75

    201
  • Waveforms for 7-bit Transmission 76

    201
  • FSR Register 12

    201
  • ADDLW 137

    201
  • ADDWF 137

    201
  • ANDLW 137

    201
  • ANDWF 137

    201
  • BCF 137

    201
  • BSF 137

    201
  • BTFSC 137

    201
  • BTFSS 137

    201
  • CALL 138

    201
  • CLRF 138

    201
  • CLRW 138

    201
  • CLRWDT 138

    201
  • COMF 138

    201
  • DECF 138

    201
  • DECFSZ 139

    201
  • GOTO 139

    201
  • INCF 139

    201
  • INCFSZ 139

    201
  • IORLW 139

    201
  • IORWF 139

    201
  • MOVF 140

    201
  • MOVLW 140

    201
  • MOVWF 140

    201
  • NOP 140

    201
  • RETFIE 140

    201
  • RETLW 140

    201
  • RETURN 141

    201
  • RLF 141

    201
  • RRF 141

    201
  • SLEEP 141

    201
  • SUBLW 141

    201
  • SUBWF 141

    201
  • SWAPF 142

    201
  • XORLW 142

    201
  • XORWF 142

    201
  • Summary Table 136

    201
  • GIE Bit 20

    201
  • INTE Bit 20

    201
  • INTF Bit 20

    201
  • PEIE Bit 20

    201
  • RBIE Bit 20

    201
  • RBIF Bit 20, 31

    201
  • T0IE Bit 20

    201
  • T0IF Bit 20

    201
  • Block Diagram 129

    201
  • Interrupt-on-Change (RB7:RB4 ) 31

    201
  • RB0/INT Pin, External 7, 8, 130

    201
  • TMR0 Overflow 130

    201
  • USART Receive/Transmit Complete 95

    201
  • Bus Collision Interrupt 24

    201
  • Synchronous Serial Port Interrupt 22

    201
  • Global Interrupt Enable (GIE Bit) 20, 129

    201
  • Interrupt-on-Change (RB7:RB4) Enable (RBIE Bit) 130

    201
  • Interrupt-on-Change (RB7:RB4) Enable (RBIE Bit) 20

    201
  • Peripheral Interrupt Enable (PEIE Bit) 20

    201
  • RB0/INT Enable (INTE Bit) 20

    201
  • TMR0 Overflow Enable (T0IE Bit) 20

    201
  • Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) 130

    201
  • Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) 20, 31

    201
  • RB0/INT Flag (INTF Bit) 20

    201
  • TMR0 Overflow Flag (T0IF Bit) 20, 130

    201
    • K

      201
    • L

      201
    • M

      201
  • MCLR Reset, Normal Operation 123, 125, 126

    201
  • MCLR Reset, SLEEP 123, 125, 126

    201
  • Data Memory 12

    201
  • Program Memory 11

    201
    • O

      202
  • INTEDG Bit 19

    202
  • PS2:PS0 Bits 19

    202
  • PSA Bit 19

    202
  • T0CS Bit 19

    202
  • T0SE Bit 19

    202
  • HS 121, 124

    202
  • LP 121, 124

    202
  • RC 121, 122, 124

    202
  • XT 121, 124

    202
  • Capacitor Selection 122

    202
  • Crystal and Ceramic Resonators 121

    202
  • RC 122

    202
    • P

      202
  • Associated Registers 39

    202
  • Block Diagram 38

    202
  • RE0/RD/AN5 Pin 9, 36, 38

    202
  • RE1/WR/AN6 Pin 9, 36, 38

    202
  • RE2/CS/AN7 Pin 9, 36, 38

    202
  • Read Waveforms 39

    202
  • Select (PSPMODE Bit) 35, 36, 37, 38

    202
  • Write Waveforms 39

    202
  • BOR Bit 25

    202
  • POR Bit 25

    202
  • PIC16F873/PIC16F876 7

    202
  • PIC16F874/PIC16F877 8

    202
  • Analog Port Pins 7, 8

    202
  • Associated Registers 30

    202
  • Block Diagram

    202
  • Initialization 29

    202
  • PORTA Register 15, 29

    202
  • RA3

    202
  • RA4/T0CKI Pin 7, 8

    202
  • RA5/SS/AN4 Pin 7, 8

    202
  • TRISA Register 29

    202
  • Associated Registers 32

    202
  • Block Diagram

    202
  • PORTB Register 15, 31

    202
  • RB0/INT Edge Select (INTEDG Bit) 19

    202
  • RB0/INT Pin, External 7, 8, 130

    202
  • RB7:RB4 Interrupt on Change 130

    202
  • RB7:RB4 Interrupt on Change Enable (RBIE Bit) 130

    202
  • RB7:RB4 Interrupt on Change Flag (RBIF Bit) 130

    202
  • RB7:RB4 Interrupt-on-Change Enable (RBIE Bit) 20

    202
  • RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) 20, 31

    202
  • TRISB Register 17, 31

    202
  • Associated Registers 34

    202
  • Block Diagrams

    202
  • PORTC Register 15, 33

    202
  • RC0/T1OSO/T1CKI Pin 7, 9

    202
  • RC1/T1OSI/CCP2 Pin 7, 9

    202
  • RC2/CCP1 Pin 7, 9

    202
  • RC3/SCK/SCL Pin 7, 9

    202
  • RC4/SDI/SDA Pin 7, 9

    202
  • RC5/SDO Pin 7, 9

    202
  • RC6/TX/CK Pin 7, 9, 96

    202
  • RC7/RX/DT Pin 7, 9, 96, 97

    202
  • TRISC Register 33, 95

    202
  • Associated Registers 35

    202
  • Block Diagram 35

    202
  • Parallel Slave Port (PSP) Function 35

    202
  • PORTD Register 15, 35

    202
  • TRISD Register 35

    202
  • Analog Port Pins 9, 36, 38

    203
  • Associated Registers 36

    203
  • Block Diagram 36

    203
  • Input Buffer Full Status (IBF Bit) 37

    203
  • Input Buffer Overflow (IBOV Bit) 37

    203
  • Output Buffer Full Status (OBF Bit) 37

    203
  • PORTE Register 15, 36

    203
  • PSP Mode Select (PSPMODE Bit) 35, 36, 37, 38

    203
  • RE0/RD/AN5 Pin 9, 36, 38

    203
  • RE1/WR/AN6 Pin 9, 36, 38

    203
  • RE2/CS/AN7 Pin 9, 36, 38

    203
  • TRISE Register 36

    203
  • Assignment (PSA Bit) 19

    203
  • Rate Select (PS2:PS0 Bits) 19

    203
  • Oscillator Start-up Timer (OST) 119, 124

    203
  • POR Status (POR Bit) 25

    203
  • Power Control (PCON) Register 124

    203
  • Power-down (PD Bit) 18, 123

    203
  • Power-up Timer (PWRT) 119, 124

    203
  • Time-out (TO Bit) 18, 123

    203
  • Time-out Sequence on Power-up 127, 128

    203
  • Assignment (PSA Bit) 19

    203
  • Rate Select (PS2:PS0 Bits) 19

    203
  • RESET Conditions 125

    203
  • Interrupt Vector 11

    203
  • Paging 11, 26

    203
  • Program Memory Map 11

    203
  • RESET Vector 11

    203
    • R

      203
  • ADDEN Bit 96

    203
  • CREN Bit 96

    203
  • FERR Bit 96

    203
  • OERR Bit 96

    203
  • RX9 Bit 96

    203
  • RX9D Bit 96

    203
  • SPEN Bit 95, 96

    203
  • SREN Bit 96

    203
  • ADCON0 (A/D Control 0) 111

    203
  • ADCON1 (A/D Control 1) 112

    203
  • CCP1CON (CCP Control 1) 58

    203
  • EECON2 41

    203
  • FSR 27

    203
  • INTCON 20

    203
  • OPTION_REG 19, 48

    203
  • PCON (Power Control) 25

    203
  • PIE1 (Peripheral Interrupt Enable 1) 21

    203
  • PIE2 (Peripheral Interrupt Enable 2) 23

    203
  • PIR1 (Peripheral Interrupt Request 1) 22

    203
  • PIR2 (Peripheral Interrupt Request 2) 24

    203
  • RCSTA (Receive Status and Control) 96

    203
  • Special Function, Summary 15

    203
  • SSPCON2 (Sync Serial Port Control 2) 68

    203
  • STATUS 18

    203
  • T1CON (Timer1 Control) 51

    203
  • T2CON (Timer 2 Control)

    203
  • TRISE 37

    203
  • TXSTA (Transmit Status and Control) 95

    203
  • Block Diagram 123

    203
  • MCLR Reset. See MCLR

    203
  • Brown-out Reset (BOR). See Brown-out Reset (BOR)

    203
  • Power-on Reset (POR). See Power-on Reset (POR)

    203
  • RESET Conditions for PCON Register 125

    203
  • RESET Conditions for Program Counter 125

    203
  • RESET Conditions for STATUS Register 125

    203
  • WDT Reset. See Watchdog Timer (WDT)

    203
    • S

      203
  • Data EEPROM and FLASH Program Memory 41

    203
  • Master Mode 70

    204
  • Master Mode Timing 70

    204
  • Serial Clock 69

    204
  • Serial Data In 69

    204
  • Serial Data Out 69

    204
  • Serial Peripheral Interface (SPI) 65

    204
  • Slave Mode Timing 71

    204
  • Slave Mode Timing Diagram 71

    204
  • Slave Select 69

    204
  • SPI Clock 70

    204
  • SPI Mode 69

    204
  • Associated Registers 72

    204
  • Slave Mode 71

    204
  • Block Diagram (SPI Mode) 69

    204
  • RA5/SS/AN4 Pin 7, 8

    204
  • RC3/SCK/SCL Pin 7, 9

    204
  • RC4/SDI/SDA Pin 7, 9

    204
  • RC5/SDO Pin 7, 9

    204
  • SPI Mode 69

    204
  • SSPADD 73, 74

    204
  • SSPBUF 70, 73

    204
  • SSPCON2 68

    204
  • SSPSR 70, 74

    204
  • SSPSTAT 73

    204
  • SSP I2C Operation 73

    204
  • SPI Master Mode 70

    204
  • SPI Slave Mode 71

    204
  • SSPCON1 Register 73

    204
  • Overflows 26

    204
  • Underflow 26

    204
  • C Bit 18

    204
  • DC Bit 18

    204
  • IRP Bit 18

    204
  • PD Bit 18, 123

    204
  • RP1:RP0 Bits 18

    204
  • TO Bit 18, 123

    204
  • Z Bit 18

    204
    • T

      204
  • Associated Registers 49

    204
  • Clock Source Edge Select (T0SE Bit) 19

    204
  • Clock Source Select (T0CS Bit) 19

    204
  • External Clock 48

    204
  • Interrupt 47

    204
  • Overflow Enable (T0IE Bit) 20

    204
  • Overflow Flag (T0IF Bit) 20, 130

    204
  • Overflow Interrupt 130

    204
  • Prescaler 48

    204
  • RA4/T0CKI Pin, External Clock 7, 8

    204
  • T0CKI 48

    204
  • WDT Prescaler Block Diagram 47

    204
  • Associated Registers 54

    204
  • Asynchronous Counter Mode 53

    204
  • Block Diagram 52

    204
  • Counter Operation 52

    204
  • Operation in Timer Mode 52

    204
  • Oscillator 53

    204
  • Prescaler 54

    204
  • RC0/T1OSO/T1CKI Pin 7, 9

    204
  • RC1/T1OSI/CCP2 Pin 7, 9

    204
  • Resetting of Timer1 Registers 54

    204
  • Resetting Timer1 using a CCP Trigger Output 53

    204
  • Synchronized Counter Mode 52

    204
  • T1CON 51

    204
  • T1CON Register 51

    204
  • TMR1H 53

    204
  • TMR1L 53

    204
  • Associated Registers 56

    204
  • Block Diagram 55

    204
  • Output 56

    204
  • Postscaler 55

    204
  • Prescaler 55

    204
  • T2CON 55

    204
  • A/D Conversion 175

    204
  • Acknowledge Sequence Timing 86

    204
  • Baud Rate Generator with Clock Arbitration 80

    204
  • BRG Reset Due to SDA Collision 91

    204
  • Brown-out Reset 164

    204
  • Bus Collision

    204
  • Bus Collision During a Repeated START Condition (Case 1) 92

    205
  • Bus Collision During a Repeated START Condition (Case2) 92

    205
  • Bus Collision During a START Condition (SCL = 0) 91

    205
  • Bus Collision During a STOP Condition 93

    205
  • Bus Collision for Transmit and Acknowledge 89

    205
  • Capture/Compare/PWM 166

    205
  • CLKOUT and I/O 163

    205
  • I2C Bus Data 171

    205
  • I2C Bus START/STOP bits 170

    205
  • I2C Master Mode First START Bit Timing 80

    205
  • I2C Master Mode Reception Timing 85

    205
  • I2C Master Mode Transmission Timing 83

    205
  • Master Mode Transmit Clock Arbitration 88

    205
  • Power-up Timer 164

    205
  • Repeat START Condition 81

    205
  • RESET 164

    205
  • SPI Master Mode 70

    205
  • SPI Slave Mode (CKE = 1) 71

    205
  • SPI Slave Mode Timing (CKE = 0) 71

    205
  • Start-up Timer 164

    205
  • STOP Condition Receive or Transmit 87

    205
  • Time-out Sequence on Power-up 127, 128

    205
  • Timer0 165

    205
  • Timer1 165

    205
  • USART Asynchronous Master Transmission 100

    205
  • USART Asynchronous Reception 102

    205
  • USART Synchronous Receive 173

    205
  • USART Synchronous Reception 108

    205
  • USART Synchronous Transmission 106, 173

    205
  • USART, Asynchronous Reception 104

    205
  • Wake-up from SLEEP via Interrupt 133

    205
  • Watchdog Timer 164

    205
  • IBF Bit 37

    205
  • IBOV Bit 37

    205
  • OBF Bit 37

    205
  • PSPMODE Bit 35, 36, 37, 38

    205
  • BRGH Bit 95

    205
  • CSRC Bit 95

    205
  • SYNC Bit 95

    205
  • TRMT Bit 95

    205
  • TX9 Bit 95

    205
  • TX9D Bit 95

    205
  • TXEN Bit 95

    205
    • U

      205
  • Address Detect Enable (ADDEN Bit) 96

    205
  • Asynchronous Mode 99

    205
  • Asynchronous Receive 101

    205
  • Asynchronous Receive (9-bit Mode) 103

    205
  • Asynchronous Receive with Address Detect. SeeAsynchronous Receive (9-bit Mode).

    205
  • Asynchronous Reception 102

    205
  • Asynchronous Transmitter 99

    205
  • Baud Rate Generator (BRG) 97

    205
  • Clock Source Select (CSRC Bit) 95

    205
  • Continuous Receive Enable (CREN Bit) 96

    205
  • Framing Error (FERR Bit) 96

    205
  • Mode Select (SYNC Bit) 95

    205
  • Overrun Error (OERR Bit) 96

    205
  • RC6/TX/CK Pin 7, 9

    205
  • RC7/RX/DT Pin 7, 9

    205
  • RCSTA Register 96

    205
  • Receive Data, 9th bit (RX9D Bit) 96

    205
  • Receive Enable, 9-bit (RX9 Bit) 96

    205
  • Serial Port Enable (SPEN Bit) 95, 96

    205
  • Single Receive Enable (SREN Bit) 96

    205
  • Synchronous Master Mode 105

    205
  • Synchronous Master Reception 107

    205
  • Synchronous Master Transmission 105

    205
  • Synchronous Slave Mode 108

    205
  • Synchronous Slave Reception 109

    205
  • Synchronous Slave Transmit 108

    205
  • Transmit Block Diagram 99

    205
  • Transmit Data, 9th Bit (TX9D) 95

    205
  • Transmit Enable (TXEN Bit) 95

    205
  • Transmit Enable, Nine-bit (TX9 Bit) 95

    205
  • Transmit Shift Register Status (TRMT Bit) 95

    205
  • TXSTA Register 95

    205
    • W

      206
  • Interrupts 125, 126

    206
  • MCLR Reset 126

    206
  • Timing Diagram 133

    206
  • WDT Reset 126

    206
  • Block Diagram 131

    206
  • Enable (WDTE Bit) 131

    206
  • Postscaler. See Postscaler, WDT

    206
  • Programming Considerations 131

    206
  • RC Oscillator 131

    206
  • Time-out Period 131

    206
  • WDT Reset, Normal Operation 123, 125, 126

    206
  • WDT Reset, SLEEP 123, 125, 126

    206
  • Data EEPROM and FLASH Program Memory 45

    206
• On-Line Support

  207
  • Connecting to the Microchip Internet Web Site

    207
• Reader Response

  208
• PIC16F87X Product Identification System

  209
  • To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

    209
  • Sales and Support

    209
    • Corporate Office

      218
    • Atlanta

      218
    • Boston

      218
    • Chicago

      218
    • Cleveland

      218
    • Fax: 216-447-0643

      218
    • Dallas

      218
    • Detroit

      218
    • Indianapolis

      218
    • Toronto

      218
    • Fax: 852-2401-3431

      218
    • Australia - Sydney

      218
    • China - Beijing

      218
    • China - Shanghai

      218
    • India - Bangalore

      218
    • Korea - Daegu

      218
    • Korea - Seoul

      218
    • Singapore

      218
    • Taiwan - Taipei

      218
    • Fax: 43-7242-2244-393

      218
    • Denmark - Copenhagen

      218
    • France - Paris

      218
    • Germany - Munich

      218
    • Italy - Milan

      218
    • Spain - Madrid

      218
    • UK - Wokingham

      218
    • Worldwide Sales and Service

      218