用户手册 — Microchip Technology MA330019

目录

• Operating Conditions

  1
• Clock Management

  1
• Core Performance

  1
• Motor Control PWM

  1
• Advanced Analog Features

  1
• Input/Output

  1
• System Peripherals

  1
• Communication Interfaces

  1
• Direct Memory Access (DMA)

  1
• Qualification and Class B Support

  1
• Debugger Development Support

  1
• Packages

  1
• dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04 Product Families

  2
  • Pin Diagrams

    3
  • Pin Diagrams (Continued)

    4
  • Pin Diagrams (Continued)

    5
  • Pin Diagrams (Continued)

    6
  • Pin Diagrams (Continued)

    7
  • Table of Contents

    8
  • Most Current Data Sheet

    9
  • Errata

    9
  • Customer Notification System

    9
  • Referenced Sources

    10
• 1.0 Device Overview

  11
  • FIGURE 1-1: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/ X04 Block Diagram

    12
  • TABLE 1-1: Pinout I/O Descriptions (Continued)

    13
• 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers

  17
  • 2.1 Basic Connection Requirements

    17
  • 2.2 Decoupling Capacitors

    17
    • FIGURE 2-1: Recommended Minimum connection

      18
    • 2.2.1 Tank Capacitors

      18
  • 2.3 CPU Logic Filter Capacitor Connection (Vcap)

    18
  • 2.4 Master Clear (MCLR) Pin

    18
    • FIGURE 2-2: Example of MCLR Pin Connections

      18
  • 2.5 ICSP Pins

    19
  • 2.6 External Oscillator Pins

    19
    • FIGURE 2-3: Suggested Placement of the Oscillator Circuit

      19
    • TABLE 2-1: Crystal Recommendations

      19
    • TABLE 2-2: Resonator Recommendations

      20
  • 2.7 Oscillator Value Conditions on Device Start-up

    20
  • 2.8 Configuration of Analog and Digital Pins During ICSP Operations

    20
  • 2.9 Unused I/Os

    20
• 3.0 CPU

  21
  • 3.1 Overview

    21
  • 3.2 Data Addressing Overview

    21
  • 3.3 DSP Engine Overview

    22
  • 3.4 Special MCU Features

    22
    • FIGURE 3-1: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/ X04 CPU Core Block Diagram

      23
    • FIGURE 3-2: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/ X04 Programmer’s Model

      24
  • 3.5 CPU Resources

    25
    • 3.5.1 Key Resources

      25
  • 3.6 CPU Control Registers

    26
    • Register 3-1: SR: CPU STATUS Register (Continued)

      26
    • Register 3-2: CORCON: CORE Control Register (Continued)

      28
  • 3.7 Arithmetic Logic Unit (ALU)

    30
    • 3.7.1 Multiplier

      30
    • 3.7.2 Divider

      30
  • 3.8 DSP Engine

    30
    • TABLE 3-1: DSP Instructions Summary

      30
    • FIGURE 3-3: DSP Engine Block Diagram

      31
    • 3.8.1 Multiplier

      32
    • 3.8.2 Data Accumulators and Adder/Subtracter

      32
    • 3.8.3 Accumulator Write Back

      33
    • 3.8.4 Barrel Shifter

      34
• 4.0 Memory Organization

  35
  • 4.1 Program Address Space

    35
    • FIGURE 4-1: Program Memory Map for dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/ X04 and dsPIC33FJ128MCX02/X04 Devices

      35
    • 4.1.1 Program Memory Organization

      36
    • 4.1.2 Interrupt and Trap Vectors

      36
      • FIGURE 4-2: Program Memory Organization

        36
  • 4.2 Data Address Space

    37
    • 4.2.1 Data Space Width

      37
    • 4.2.2 Data Memory Organization and Alignment

      37
    • 4.2.3 SFR Space

      37
    • 4.2.4 Near Data Space

      37
      • FIGURE 4-3: Data Memory Map for dsPIC33FJ32MC302/304 Devices with 4 Kb RAM

        38
      • FIGURE 4-4: Data Memory Map for dsPIC33FJ128MC202/204 and dsPIC33FJ64MC202/ 204 Devices with 8 Kb RAM

        39
      • FIGURE 4-5: Data Memory Map for dsPIC33FJ128MC802/804 And dsPIC33FJ64MC802/ 804 Devices with 16 Kb RAM

        40
    • 4.2.5 X and Y Data Spaces

      41
    • 4.2.6 DMA RAM

      41
  • 4.3 Memory Resources

    41
    • 4.3.1 Key Resources

      41
  • 4.4 Special Function Register Maps

    42
    • TABLE 4-1: CPU Core Registers Map (Continued)

      42
    • TABLE 4-2: Change Notification Register Map for dsPIC33FJ128MC202/802, dsPIC33FJ64MC202/802 and dsPIC33FJ32MC302

      44
    • TABLE 4-3: Change Notification Register Map for dsPIC33FJ128MC204/804, dsPIC33FJ64MC204/804 and dsPIC33FJ32MC304

      44
    • TABLE 4-4: Interrupt Controller Register Map

      45
    • TABLE 4-5: Timer Register Map

      46
    • TABLE 4-6: Input Capture Register Map

      46
    • TABLE 4-7: Output Compare Register Map

      47
    • TABLE 4-8: 6-Output PWM1 Register Map

      47
    • TABLE 4-9: 2-Output PWM2 Register Map

      48
    • TABLE 4-10: QEI1 Register Map

      48
    • TABLE 4-11: QEI2 Register Map

      48
    • TABLE 4-12: I2C1 Register Map

      49
    • TABLE 4-13: UART1 Register Map

      49
    • TABLE 4-14: UART2 Register Map

      49
    • TABLE 4-15: SPI1 Register Map

      50
    • TABLE 4-16: SPI2 Register Map

      50
    • TABLE 4-17: ADC1 Register Map For dsPIC33FJ64MC202/802, dsPIC33FJ128MC202/802 AND dsPIC33FJ32MC302

      50
    • TABLE 4-18: ADC1 Register Map FOR dsPIC33FJ64MC204/804, dsPIC33FJ128MC204/804 AND dsPIC33FJ32MC304

      51
    • TABLE 4-19: DAC1 Register Map For dsPIC33FJ128MC804 and dsPIC33FJ64MC804

      51
    • TABLE 4-20: dma Register Map (Continued)

      52
    • TABLE 4-21: ECAN1 Register Map When C1CTRL1.WIN = 0 or 1 (For dsPIC33FJ128MC802/804 and dsPIC33FJ64MC802/804)

      54
    • TABLE 4-22: ECAN1 Register Map When C1CTRL1.WIN = 0 (For dsPIC33FJ128MC802/804 and dsPIC33FJ64MC802/804)

      54
    • TABLE 4-23: ECAN1 Register Map When C1CTRL1.WIN = 1 (For dsPIC33FJ128MC802/804 and dsPIC33FJ64MC802/804) (Continued)

      55
    • TABLE 4-24: PERIPHERAL pin select INPUT Register Map

      57
    • TABLE 4-25: PERIPHERAL pin select outPUT Register Map FOR dsPIC33FJ128MC202/802, dsPIC33FJ64MC202/802 AND dsPIC33FJ32MC302

      58
    • TABLE 4-26: PERIPHERAL pin select outPUT Register Map For dsPIC33FJ128MC204/804, dsPIC33FJ64MC204/804 AND dsPIC33FJ32MC304

      58
    • TABLE 4-27: Parallel Master/Slave Port Register Map For dsPIC33FJ128MC202/802, dsPIC33FJ64MC202/802 AND dsPIC33FJ32MC302

      59
    • TABLE 4-28: Parallel Master/Slave Port Register Map For dsPIC33FJ128MC204/804, dsPIC33FJ64MC204/804 AND dsPIC33FJ32MC304

      59
    • TABLE 4-29: Real-Time Clock and Calendar Register Map

      60
    • TABLE 4-30: CRC Register Map

      60
    • TABLE 4-31: Dual Comparator Register Map

      60
    • TABLE 4-32: PORTA Register Map For dsPIC33FJ128MC202/802, dsPIC33FJ64MC202/802 AND dsPIC33FJ32MC302

      60
    • TABLE 4-33: PORTA Register Map For dsPIC33FJ128MC204/804, dsPIC33FJ64MC204/804 AND dsPIC33FJ32MC304

      61
    • TABLE 4-34: PORTB Register Map

      61
    • TABLE 4-35: PORTC Register Map For dsPIC33FJ128MC204/804, dsPIC33FJ64MC204/804 And dsPIC33FJ32MC304

      61
    • TABLE 4-36: System Control Register Map

      61
    • TABLE 4-37: sECURITY Register Map for dsPIC33FJ128MC204/804 and dsPIC33FJ64MC204/804 Only

      62
    • TABLE 4-38: NVM Register Map

      62
    • TABLE 4-39: pmd Register Map

      62
    • 4.4.1 Software Stack

      63
      • FIGURE 4-6: CALL Stack Frame

        63
    • 4.4.2 Data Ram Protection Feature

      63
  • 4.5 Instruction Addressing Modes

    63
    • 4.5.1 File Register Instructions

      63
    • 4.5.2 MCU Instructions

      63
      • TABLE 4-40: Fundamental Addressing Modes Supported

        64
    • 4.5.3 Move and Accumulator Instructions

      64
    • 4.5.4 MAC Instructions

      64
    • 4.5.5 Other Instructions

      64
  • 4.6 Modulo Addressing

    65
    • 4.6.1 Start and End Address

      65
    • 4.6.2 W Address Register Selection

      65
      • FIGURE 4-7: Modulo Addressing Operation Example

        65
    • 4.6.3 Modulo Addressing Applicability

      66
  • 4.7 Bit-Reversed Addressing

    66
    • 4.7.1 Bit-Reversed Addressing Implementation

      66
      • FIGURE 4-8: Bit-Reversed Address Example

        67
      • TABLE 4-41: Bit-Reversed Address Sequence (16-Entry)

        67
  • 4.8 Interfacing Program and Data Memory Spaces

    68
    • 4.8.1 Addressing Program Space

      68
      • TABLE 4-42: Program Space Address Construction

        68
      • FIGURE 4-9: Data Access from Program Space Address Generation

        69
    • 4.8.2 Data Access From Program Memory Using Table Instructions

      70
      • FIGURE 4-10: Accessing Program Memory with Table Instructions

        70
    • 4.8.3 Reading Data from Program Memory Using Program Space Visibility

      71
      • FIGURE 4-11: Program Space Visibility Operation

        71
• 5.0 Flash Program Memory

  73
  • 5.1 Table Instructions and Flash Programming

    73
    • FIGURE 5-1: Addressing for Table Registers

      73
  • 5.2 RTSP Operation

    74
  • 5.3 Programming Operations

    74
    • EQUATION 5-1: Programming Time

      74
    • EQUATION 5-2: Minimum Row Write Time

      74
    • EQUATION 5-3: Maximum Row Write Time

      74
  • 5.4 Control Registers

    74
  • 5.5 Flash Programming Resources

    74
    • 5.5.1 Key Resources

      74
  • 5.6 Flash Memory Control Registers

    75
    • Register 5-1: NVMCON: Flash Memory Control Register

      75
    • Register 5-2: NVMKEY: NonVolatile Memory Key RegisteR

      76
    • 5.6.1 Programming Algorithm for Flash Program Memory

      77
      • EXAMPLE 5-1: Erasing a Program Memory Page

        77
      • EXAMPLE 5-2: Loading the Write Buffers

        78
      • EXAMPLE 5-3: Initiating a Programming Sequence

        78
• 6.0 Resets

  79
  • FIGURE 6-1: Reset System Block Diagram

    79
  • 6.1 Resets Resources

    80
    • 6.1.1 Key Resources

      80
  • 6.2 Reset Control Registers

    81
    • Register 6-1: RCON: Reset Control Register(1) (Continued)

      81
  • 6.3 System Reset

    83
    • TABLE 6-1: Oscillator Delay

      83
    • FIGURE 6-2: System Reset Timing

      84
    • TABLE 6-2: Oscillator Parameters

      85
  • 6.4 Power-on Reset (POR)

    85
  • 6.4.1 Brown-out Reset (BOR) and Power-up Timer (PWRT)

    85
    • FIGURE 6-3: Brown-out Situations

      86
  • 6.5 External Reset (EXTR)

    86
    • 6.5.0.1 External supervisory circuit

      86
    • 6.5.0.2 Internal Supervisory Circuit

      86
  • 6.6 Software RESET Instruction (SWR)

    86
  • 6.7 Watchdog Time-out Reset (WDTO)

    86
  • 6.8 Trap Conflict Reset

    86
  • 6.9 Configuration Mismatch Reset

    87
  • 6.10 Illegal Condition Device Reset

    87
    • 6.10.0.1 Illegal Opcode Reset

      87
    • 6.10.0.2 Uninitialized W Register Reset

      87
    • 6.10.0.3 Security Reset

      87
  • 6.11 Using the RCON Status Bits

    87
    • TABLE 6-3: Reset Flag Bit Operation(1)

      87
• 7.0 Interrupt Controller

  89
  • 7.1 Interrupt Vector Table

    89
    • 7.1.1 Alternate Interrupt Vector Table

      89
  • 7.2 Reset Sequence

    89
    • FIGURE 7-1: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/ X04 Interrupt Vector Table

      90
    • TABLE 7-1: Interrupt Vectors (Continued)

      91
  • 7.3 Interrupt Control and Status Registers

    93
    • 7.3.1 INTCON1 and INTCON2

      93
    • 7.3.2 IFSx

      93
    • 7.3.3 IECx

      93
    • 7.3.4 IPCx

      93
    • 7.3.5 INTTREG

      93
    • 7.3.6 status/Control registers

      93
  • 7.4 Interrupts Resources

    93
    • 7.4.1 Key Resources

      93
  • 7.5 Interrupt Registers

    94
    • Register 7-1: SR: CPU STATUS Register(1)

      94
    • Register 7-2: CORCON: CORE Control Register(1)

      94
    • Register 7-3: INTCON1: Interrupt Control Register 1 (Continued)

      95
    • Register 7-4: INTCON2: Interrupt Control Register 2

      97
    • Register 7-5: IFS0: Interrupt Flag Status Register 0 (Continued)

      98
    • Register 7-6: IFS1: Interrupt Flag Status Register 1 (Continued)

      100
    • Register 7-7: IFS2: Interrupt Flag Status Register 2

      102
    • Register 7-8: IFS3: Interrupt Flag Status Register 3

      103
    • Register 7-9: IFS4: Interrupt Flag Status Register 4

      104
    • Register 7-10: IEC0: Interrupt Enable Control Register 0 (Continued)

      105
    • Register 7-11: IEC1: Interrupt Enable Control Register 1 (Continued)

      107
    • Register 7-12: IEC2: Interrupt Enable Control Register 2

      109
    • Register 7-13: IEC3: Interrupt Enable Control Register 3

      110
    • Register 7-14: IEC4: Interrupt Enable Control Register 4

      111
    • Register 7-15: IPC0: Interrupt Priority Control Register 0

      112
    • Register 7-16: IPC1: Interrupt Priority Control Register 1

      113
    • Register 7-17: IPC2: Interrupt Priority Control Register 2

      114
    • Register 7-18: IPC3: Interrupt Priority Control Register 3

      115
    • Register 7-19: IPC4: Interrupt Priority Control Register 4

      116
    • Register 7-20: IPC5: Interrupt Priority Control Register 5

      117
    • Register 7-21: IPC6: Interrupt Priority Control Register 6

      118
    • Register 7-22: IPC7: Interrupt Priority Control Register 7

      119
    • Register 7-23: IPC8: Interrupt Priority Control Register 8

      120
    • Register 7-24: IPC9: Interrupt Priority Control Register 9

      121
    • Register 7-25: IPC11: Interrupt Priority Control Register 11

      122
    • Register 7-26: IPC14: Interrupt Priority Control Register 14

      123
    • Register 7-27: IPC15: Interrupt Priority Control Register 15

      124
    • Register 7-28: IPC16: Interrupt Priority Control Register 16

      125
    • Register 7-29: IPC17: Interrupt Priority Control Register 17

      126
    • Register 7-30: IPC18: Interrupt Priority Control Register 18

      127
    • Register 7-31: IPC19: Interrupt Priority Control Register 19

      128
    • Register 7-32: INTTREG: Interrupt Control and Status Register

      129
  • 7.6 Interrupt Setup Procedures

    130
    • 7.6.1 Initialization

      130
    • 7.6.2 Interrupt Service Routine

      130
    • 7.6.3 Trap Service Routine

      130
    • 7.6.4 Interrupt Disable

      130
• 8.0 Direct Memory Access (DMA)

  131
  • TABLE 8-1: DMA Channel to Peripheral Associations

    131
  • FIGURE 8-1: Top Level System Architecture Using a Dedicated Transaction Bus

    132
  • 8.1 DMA Resources

    133
    • 8.1.1 Key Resources

      133
  • 8.2 DMAC Registers

    133
    • Register 8-1: DMAxCON: DMA Channel x Control Register

      134
    • Register 8-2: DMAxREQ: DMA Channel x IRQ Select Register

      135
    • Register 8-3: DMAxSTA: DMA Channel x RAM Start Address Register A(1)

      136
    • Register 8-4: DMAxSTB: DMA Channel x RAM Start Address Register B(1)

      136
    • Register 8-5: DMAxPAD: DMA Channel x Peripheral Address Register(1)

      137
    • Register 8-6: DMAxCNT: DMA Channel x Transfer Count Register(1)

      137
    • Register 8-7: DMACS0: DMA Controller Status Register 0 (Continued)

      138
    • Register 8-8: DMACS1: DMA Controller Status Register 1

      140
    • Register 8-9: DSADR: Most Recent DMA RAM Address

      141
• 9.0 Oscillator Configuration

  143
  • FIGURE 9-1: Oscillator System Diagram

    143
  • 9.1 CPU Clocking System

    144
    • 9.1.1 System Clock Sources

      144
    • 9.1.2 System Clock Selection

      144
      • EQUATION 9-1: Device Operating Frequency

        144
    • 9.1.3 Auxiliary Oscillator

      144
    • 9.1.4 PLL Configuration

      145
      • EQUATION 9-2: Fosc Calculation

        145
      • EQUATION 9-3: XT with PLL Mode Example

        145
      • FIGURE 9-2: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/ X04 PLL Block Diagram

        145
      • TABLE 9-1: Configuration Bit Values for Clock Selection

        146
  • 9.2 Oscillator Resources

    146
    • 9.2.1 Key Resources

      146
  • 9.3 Oscillator Control Registers

    147
    • Register 9-1: OSCCON: Oscillator Control Register(1,3) (Continued)

      147
    • Register 9-2: CLKDIV: Clock Divisor Register(2)

      149
    • Register 9-3: PLLFBD: PLL Feedback Divisor Register(1)

      150
    • Register 9-4: OSCTUN: FRC Oscillator Tuning Register(2)

      151
    • Register 9-5: ACLKCON: Auxiliary Clock Divisor Control Register(1)

      152
  • 9.4 Clock Switching Operation

    153
    • 9.4.1 Enabling Clock Switching

      153
    • 9.4.2 Oscillator Switching Sequence

      153
  • 9.5 Fail-Safe Clock Monitor (FSCM)

    153
• 10.0 Power-Saving Features

  155
  • 10.1 Clock Frequency and Clock Switching

    155
  • 10.2 Instruction-Based Power-Saving Modes

    155
    • 10.2.1 Sleep Mode

      155
      • EXAMPLE 10-1: PWRSAV Instruction Syntax

        155
    • 10.2.2 Idle Mode

      156
    • 10.2.3 Interrupts Coincident with Power Save Instructions

      156
  • 10.3 Doze Mode

    156
  • 10.4 Peripheral Module Disable

    156
  • 10.5 Power-Saving Resources

    157
    • 10.5.1 Key Resources

      157
  • 10.6 Power-Saving Registers

    158
    • Register 10-1: PMD1: Peripheral Module Disable Control Register 1 (Continued)

      158
    • Register 10-2: PMD2: Peripheral Module Disable Control Register 2

      160
    • Register 10-3: PMD3: Peripheral Module Disable Control Register 3

      161
• 11.0 I/O Ports

  163
  • 11.1 Parallel I/O (PIO) Ports

    163
    • FIGURE 11-1: Block Diagram of a Typical Shared Port Structure

      163
  • 11.2 Open-Drain Configuration

    164
  • 11.3 Configuring Analog Port Pins

    164
  • 11.4 I/O Port Write/Read Timing

    164
  • 11.5 Input Change Notification

    164
    • EXAMPLE 11-1: Port Write/Read Example

      164
  • 11.6 Peripheral Pin Select

    165
    • 11.6.1 Available Pins

      165
    • 11.6.2 Controlling Peripheral Pin Select

      165
      • FIGURE 11-2: remappable MUX input for u1rx

        165
      • TABLE 11-1: Selectable INPUT SOURCES (MAPS Input TO FUNCTION)(1)

        166
      • FIGURE 11-3: multiplexing of remappable output for rpn

        167
      • TABLE 11-2: OUTPUT selection for remappable pin (RPn)

        167
    • 11.6.3 Controlling Configuration Changes

      168
  • 11.7 I/O Helpful Tips

    169
  • 11.8 I/O Resources

    169
    • 11.8.1 Key Resources

      169
  • 11.9 Peripheral Pin Select Registers

    170
    • Register 11-1: RPINR0: Peripheral Pin Select Input Register 0

      170
    • Register 11-2: RPINR1: Peripheral Pin Select Input Register 1

      171
    • Register 11-3: RPINR3: Peripheral Pin Select Input Register 3

      172
    • Register 11-4: RPINR4: Peripheral Pin Select Input Register 4

      173
    • Register 11-5: RPINR7: Peripheral Pin Select Input Register 7

      174
    • Register 11-6: RPINR10: Peripheral Pin Select Input Registers 10

      175
    • Register 11-7: RPINR11: Peripheral Pin Select Input Register 11

      176
    • Register 11-8: RPINR12: Peripheral Pin Select Input Register 12

      176
    • Register 11-9: RPINR13: Peripheral Pin Select Input Register 13

      177
    • Register 11-10: RPINR14: Peripheral Pin Select INPUT Registers 14

      178
    • Register 11-11: RPINR15: Peripheral Pin Select Input Register 15

      179
    • Register 11-12: RPINR16: Peripheral Pin Select INPUT Registers 16

      180
    • Register 11-13: RPINR17: Peripheral Pin Select Input Register 17

      181
    • Register 11-14: RPINR18: Peripheral Pin Select Input Register 18

      182
    • Register 11-15: RPINR19: Peripheral Pin Select Input Register 19

      183
    • Register 11-16: RPINR20: Peripheral Pin Select Input Register 20

      184
    • Register 11-17: RPINR21: Peripheral Pin Select Input Register 21

      185
    • Register 11-18: RPINR22: Peripheral Pin Select Input Register 22

      186
    • Register 11-19: RPINR23: Peripheral Pin Select Input Register 23

      187
    • Register 11-20: RPINR26: Peripheral Pin Select Input Register 26(1)

      187
    • Register 11-21: RPOR0: Peripheral Pin Select Output Register 0

      188
    • Register 11-22: RPOR1: Peripheral Pin Select Output Register 1

      188
    • Register 11-23: RPOR2: Peripheral Pin Select Output Register 2

      189
    • Register 11-24: RPOR3: Peripheral Pin Select Output Register 3

      189
    • Register 11-25: RPOR4: Peripheral Pin Select Output Register 4

      190
    • Register 11-26: RPOR5: Peripheral Pin Select Output Register 5

      190
    • Register 11-27: RPOR6: Peripheral Pin Select Output Register 6

      191
    • Register 11-28: RPOR7: Peripheral Pin Select Output Register 7

      191
    • Register 11-29: RPOR8: Peripheral Pin Select Output Register 8(1)

      192
    • Register 11-30: RPOR9: Peripheral Pin Select Output Register 9(1)

      192
    • Register 11-31: RPOR10: Peripheral Pin Select Output Register 10(1)

      193
    • Register 11-32: RPOR11: Peripheral Pin Select Output Register 11(1)

      193
    • Register 11-33: RPOR12: Peripheral Pin Select Output Register 12(1)

      194
• 12.0 Timer1

  195
  • TABLE 12-1: Timer Mode Settings

    195
  • FIGURE 12-1: 16-bit Timer1 Module Block Diagram

    195
  • 12.1 Timer Resources

    196
    • 12.1.1 Key Resources

      196
  • 12.2 Timer1 Control Register

    197
    • Register 12-1: T1CON: Timer1 Control Register

      197
• 13.0 Timer2/3 And TImer4/5

  199
  • FIGURE 13-1: tYPE b Timer Block Diagram (x = 2 or 4)

    199
  • FIGURE 13-2: tYPE c Timer Block Diagram (X = 3 OR 5)

    199
  • TABLE 13-1: Timer Mode Settings

    200
  • 13.1 16-bit Operation

    200
  • 13.2 32-bit Operation

    200
    • TABLE 13-2: 32-bit Timer

      200
    • FIGURE 13-3: 32-bit tIMER Block Diagram

      201
  • 13.3 Timer Resources

    201
    • 13.3.1 Key Resources

      201
  • 13.4 Timer Control Registers

    202
    • Register 13-1: TxCON: Timer Control Register (x = 2 or 4)

      202
    • Register 13-2: TyCON: Timer Control Register (y = 3 or 5)

      203
• 14.0 Input Capture

  205
  • FIGURE 14-1: Input Capture Block Diagram

    205
  • 14.1 Input Capture Resources

    206
    • 14.1.1 Key Resources

      206
  • 14.2 Input Capture Registers

    207
    • Register 14-1: ICxCON: Input Capture x Control Register (x = 1, 2, 7 or 8)

      207
• 15.0 Output Compare

  209
  • FIGURE 15-1: Output Compare Module Block Diagram

    209
  • 15.1 Output Compare Modes

    210
    • TABLE 15-1: Output Compare Modes

      210
    • FIGURE 15-2: Output Compare Operation

      210
  • 15.2 Output Compare Resources

    211
    • 15.2.1 Key Resources

      211
  • 15.3 Output Compare Registers

    212
    • Register 15-1: OCxCON: Output Compare x Control Register (x = 1, 2, 3 or 4)

      212
• 16.0 Motor Control PWM Module

  213
  • 16.1 PWM1: 6-Channel PWM Module

    213
  • 16.2 PWM2: 2-Channel PWM Module

    213
    • FIGURE 16-1: 6-Channel PWM Module Block Diagram (PWM1)

      214
    • FIGURE 16-2: 2-Channel PWM Module Block Diagram (PWM2)

      215
  • 16.3 Motor Control PWM Resources

    216
    • 16.3.1 Key Resources

      216
  • 16.4 PWM Control Registers

    217
    • Register 16-1: PxTCON: PWM Time Base Control Register

      217
    • Register 16-2: PxTMR: PWM Timer Count Value Register

      218
    • Register 16-3: PxTPER: PWM Time Base Period Register

      218
    • Register 16-4: PxSECMP: Special Event Compare Register

      219
    • Register 16-5: PWMXCON1: PWM Control Register 1(2)

      220
    • Register 16-6: PWMxCON2: PWM Control Register 2

      221
    • Register 16-7: PxDTCON1: Dead-Time Control Register 1

      222
    • Register 16-8: PxDTCON2: Dead-Time Control Register 2(1)

      223
    • Register 16-9: PxFLTACON: Fault A Control Register(1)

      224
    • Register 16-10: PxOVDCON: Override Control Register(1)

      225
    • Register 16-11: PxDC1: PWM Duty Cycle Register 1

      226
    • Register 16-12: P1DC2: PWM Duty Cycle Register 2

      226
    • Register 16-13: P1DC3: PWM Duty Cycle Register 3

      226
• 17.0 Quadrature Encoder Interface (QEI) Module

  227
  • FIGURE 17-1: Quadrature Encoder Interface Block Diagram (x = 1 or 2)

    227
  • 17.1 QEI Resources

    228
    • 17.1.1 Key Resources

      228
  • 17.2 QEI Control Registers

    229
    • Register 17-1: QEIxCON: QEIx Control Register (x = 1 or 2) (Continued)

      229
    • Register 17-2: DFLTxCON: Digital Filter Control Register

      231
• 18.0 Serial Peripheral Interface (SPI)

  233
  • FIGURE 18-1: SPI Module Block Diagram

    233
  • 18.1 SPI Helpful Tips

    234
  • 18.2 SPI Resources

    234
    • 18.2.1 Key Resources

      234
  • 18.3 SPI Control Registers

    235
    • Register 18-1: SPIxSTAT: SPIx Status and Control Register

      235
    • Register 18-2: SPIxCON1: SPIx Control Register 1 (Continued)

      236
    • Register 18-3: SPIxCON2: SPIx Control Register 2

      238
• 19.0 Inter-Integrated Circuit™ (I2C™)

  239
  • 19.1 Operating Modes

    239
    • FIGURE 19-1: I2C™ Block Diagram (x = 1)

      240
  • 19.2 I2C Resources

    241
    • 19.2.1 Key Resources

      241
  • 19.3 I2C Registers

    241
    • Register 19-1: I2CxCON: I2Cx Control Register (Continued)

      242
    • Register 19-2: I2CxSTAT: I2Cx Status Register (Continued)

      244
    • Register 19-3: I2CxMSK: I2Cx Slave Mode Address Mask Register

      246
• 20.0 Universal Asynchronous Receiver Transmitter (UART)

  247
  • FIGURE 20-1: UART Simplified Block Diagram

    247
  • 20.1 UART Helpful Tips

    248
  • 20.2 UART Resources

    248
    • 20.2.1 Key Resources

      248
  • 20.3 UART Control Registers

    249
    • Register 20-1: UxMODE: UARTx Mode Register (Continued)

      249
    • Register 20-2: UxSTA: UARTx Status and Control Register (Continued)

      251
• 21.0 Enhanced CAN (ECAN™) Module

  253
  • 21.1 Overview

    253
  • 21.2 Frame Types

    254
    • FIGURE 21-1: ECAN™ Module Block Diagram

      255
  • 21.3 Modes of Operation

    256
    • 21.3.1 Initialization Mode

      256
    • 21.3.2 Disable Mode

      256
    • 21.3.3 Normal Operation Mode

      256
    • 21.3.4 Listen Only Mode

      256
    • 21.3.5 Listen All Messages Mode

      256
    • 21.3.6 Loopback Mode

      256
  • 21.4 ECAN Resources

    257
    • 21.4.1 Key Resources

      257
  • 21.5 ECAN Control Registers

    258
    • Register 21-1: CiCTRL1: ECAN™ CONTROL REGISTER 1

      258
    • Register 21-2: CiCTRL2: ECAN™ Control Register 2

      259
    • Register 21-3: CiVEC: ECAN™ Interrupt Code Register

      260
    • Register 21-4: CiFCTRL: ECAN™ FIFO Control Register

      261
    • Register 21-5: CiFIFO: ECAN™ FIFO Status Register

      262
    • Register 21-6: CiINTF: ECAN™ Interrupt Flag Register

      263
    • Register 21-7: CiINTE: ECAN™ Interrupt Enable Register

      264
    • Register 21-8: CiEC: ECAN™ Transmit/Receive Error Count Register

      265
    • Register 21-9: CiCFG1: ECAN™ Baud Rate Configuration Register 1

      265
    • Register 21-10: CiCFG2: ECAN™ Baud Rate Configuration Register 2

      266
    • Register 21-11: CiFEN1: ECAN™ Acceptance Filter Enable Register

      267
    • Register 21-12: CiBUFPNT1: ECAN™ Filter 0-3 Buffer Pointer Register

      267
    • Register 21-13: CiBUFPNT2: ECAN™ Filter 4-7 Buffer Pointer Register

      268
    • Register 21-14: CiBUFPNT3: ECAN™ Filter 8-11 Buffer Pointer Register

      268
    • Register 21-15: CiBUFPNT4: ECAN™ Filter 12-15 Buffer Pointer Register

      269
    • Register 21-16: CiRXFnSID: ECAN™ Acceptance Filter Standard Identifier Register n (n = 0-15)

      270
    • Register 21-17: CiRXFnEID: ECAN™ Acceptance Filter Extended Identifier Register n (n = 0-15)

      271
    • Register 21-18: CiFMSKSEL1: ECAN™ Filter 7-0 Mask Selection Register

      271
    • Register 21-19: CiFMSKSEL2: ECAN™ Filter 15-8 Mask Selection Register

      272
    • Register 21-20: CiRXMnSID: ECAN™ Acceptance Filter Mask Standard Identifier Register n (n = 0-2)

      273
    • Register 21-21: CiRXMnEID: ECAN™ Acceptance Filter Mask Extended Identifier Register n (n = 0-2)

      273
    • Register 21-22: CiRXFUL1: ECAN™ Receive Buffer Full Register 1

      274
    • Register 21-23: CiRXFUL2: ECAN™ Receive Buffer Full Register 2

      274
    • Register 21-24: CiRXOVF1: ECAN™ Receive Buffer Overflow Register 1

      275
    • Register 21-25: CiRXOVF2: ECAN™ Receive Buffer Overflow Register 2

      275
    • Register 21-26: CiTRmnCON: ECAN™ TX/RX Buffer m Control Register (m = 0,2,4,6; n = 1,3,5,7)

      276
  • 21.6 ECAN Message Buffers

    277
• 22.0 10-bit/12-bit Analog-to- Digital Converter (ADC1)

  281
  • 22.1 Key Features

    281
  • 22.2 ADC Initialization

    281
  • 22.3 ADC and DMA

    281
    • FIGURE 22-1: ADC Module Block Diagram FOR dsPIC33FJ32MC304, dsPIC33FJ64MC204/804 and dsPIC33FJ128MC204/804 Devices

      282
    • FIGURE 22-2: ADC1 Module Block Diagram FOR dsPIC33FJ32MC302, dsPIC33FJ64MC202/802 and dsPIC33FJ128MC202/802 Devices

      283
    • FIGURE 22-3: ADC Conversion Clock Period Block Diagram

      284
  • 22.4 ADC Helpful Tips

    285
  • 22.5 ADC Resources

    285
    • 22.5.1 Key Resources

      285
  • 22.6 ADC Control Registers

    286
    • Register 22-1: AD1CON1: ADC1 control register 1 (Continued)

      286
    • Register 22-2: AD1CON2: ADC1 control register 2

      288
    • Register 22-3: AD1CON3: ADC1 Control Register 3

      289
    • Register 22-4: AD1CON4: ADC1 Control Register 4

      290
    • Register 22-5: AD1CHS123: ADC1 INPUT Channel 1, 2, 3 select Register (Continued)

      291
    • Register 22-6: AD1CHS0: ADC1 INPUT Channel 0 select Register (Continued)

      293
    • Register 22-7: AD1CSSL: ADC1 INPUT SCAN SELECT register Low(1,2)

      295
    • Register 22-8: AD1PCFGL: ADC1 Port configuration register Low(1,2,3)

      295
• 23.0 Audio Digital-to-Analog Converter (DAC)

  297
  • 23.1 KEY FEATURES

    297
  • 23.2 DAC Module Operation

    297
  • 23.3 DAC Output Format

    297
  • 23.4 DAC CLOCK

    298
    • FIGURE 23-1: Block Diagram of Audio Digital-to-Analog Converter (DAC)

      298
    • FIGURE 23-2: Audio DAC output for Ramp Input (Unsigned)

      298
  • 23.5 DAC Resources

    299
    • 23.5.1 Key Resources

      299
  • 23.6 DAC Control Registers

    300
    • Register 23-1: DAC1CON: DAC Control Register

      300
    • Register 23-2: DAC1STAT: DAC Status Register

      301
    • Register 23-3: DAC1DFLT: DAC Default Data Register

      302
    • Register 23-4: DAC1LDAT: DAC Left Data Register

      302
    • Register 23-5: DAC1RDAT: DAC Right Data Register

      302
• 24.0 Comparator Module

  303
  • FIGURE 24-1: Comparator I/O Operating Modes

    303
  • 24.1 Comparator Resources

    304
    • 24.1.1 Key Resources

      304
  • 24.2 Comparator Control Register

    305
    • Register 24-1: CMCON: Comparator Control Register (Continued)

      305
  • 24.3 Comparator Voltage Reference

    307
    • 24.3.1 Configuring the Comparator Voltage Reference

      307
      • FIGURE 24-2: Comparator Voltage Reference Block Diagram

        307
      • Register 24-2: CVRCON: Comparator Voltage Reference Control Register

        308
• 25.0 Real-Time Clock and Calendar (RTCC)

  309
  • FIGURE 25-1: RTCC Block Diagram

    309
  • 25.1 RTCC Module Registers

    310
    • 25.1.1 Register Mapping

      310
      • TABLE 25-1: RTCVAL Register Mapping

        310
      • TABLE 25-2: ALRMVAL Register Mapping

        310
    • 25.1.2 Write Lock

      310
      • EXAMPLE 25-1: Setting the RTCWREN Bit

        310
  • 25.2 RTCC Resources

    311
    • 25.2.1 Key Resources

      311
  • 25.3 RTCC Registers

    312
    • Register 25-1: RCFGCAL: RTCC Calibration and Configuration RegistER(1) (Continued)

      312
    • Register 25-2: PADCFG1: Pad Configuration Control Register

      314
    • Register 25-3: ALCFGRPT: Alarm Configuration Register

      315
    • Register 25-4: RTCVAL (when RTCPTR<1:0> = 11): YEAR VALUE Register(1)

      316
    • Register 25-5: RTCVAL (when RTCPTR<1:0> = 10): MONTH AND DAY VALUE Register(1)

      316
    • Register 25-6: RTCVAL (when RTCPTR<1:0> = 01): WKDYHR: Weekday and Hours Value Register(1)

      317
    • Register 25-7: RTCVAL (when RTCPTR<1:0> = 00): Minutes and Seconds Value Register

      317
    • Register 25-8: ALRMVAL (when ALRMPTR<1:0> = 10): Alarm Month and Day Value Register(1)

      318
    • Register 25-9: ALRMVAL (when ALRMPTR<1:0> = 01): Alarm Weekday and Hours Value Register(1)

      318
    • Register 25-10: ALRMVAL (when ALRMPTR<1:0> = 00): Alarm Minutes and Seconds Value Register

      319
• 26.0 Programmable Cyclic Redundancy Check (CRC) Generator

  321
  • 26.1 Overview

    321
    • EQUATION 26-1: CRC equation

      321
    • TABLE 26-1: Example CRC Setup

      321
    • FIGURE 26-1: CRC Shifter Details

      321
    • FIGURE 26-2: CRC Generator Reconfigured for x16 + x12 + x5 + 1

      322
  • 26.2 User Interface

    322
    • 26.2.1 Data Interface

      322
    • 26.2.2 Interrupt Operation

      322
  • 26.3 Operation in Power-Saving Modes

    322
    • 26.3.1 Sleep Mode

      322
    • 26.3.2 Idle Mode

      322
  • 26.4 Programmable CRC Resources

    323
    • 26.4.1 Key Resources

      323
  • 26.5 Programmable CRC Registers

    324
    • Register 26-1: CRCCON: CRC Control Register

      324
    • Register 26-2: CRCXOR: CRC XOR Polynomial Register

      325
• 27.0 Parallel Master Port (PMP)

  327
  • FIGURE 27-1: PMP Module Overview

    327
  • 27.1 PMP Resources

    328
    • 27.1.1 Key Resources

      328
  • 27.2 PMP Control Registers

    329
    • Register 27-1: PMCON: Parallel Port Control Register (Continued)

      329
    • Register 27-2: PMMODE: PARALLEL PORT MODE REGISTER

      331
    • Register 27-3: PMADDR: Parallel Port Address Register

      332
    • Register 27-4: PMAEN: Parallel Port Enable Register

      332
    • Register 27-5: PMSTAT: Parallel Port Status Register

      333
    • Register 27-6: PADCFG1: Pad Configuration Control Register

      334
• 28.0 Special Features

  335
  • 28.1 Configuration Bits

    335
    • TABLE 28-1: Device Configuration Register Map

      335
    • TABLE 28-2: dsPIC33F Configuration Bits Description (Continued)

      336
  • 28.2 On-Chip Voltage Regulator

    339
    • FIGURE 28-1: Connections for the On-Chip Voltage Regulator(1,2,3)

      339
  • 28.3 Brown-Out Reset (BOR)

    339
  • 28.4 Watchdog Timer (WDT)

    340
    • 28.4.1 Prescaler/Postscaler

      340
    • 28.4.2 Sleep and Idle Modes

      340
    • 28.4.3 Enabling WDT

      340
      • FIGURE 28-2: WDT Block diagram

        340
  • 28.5 JTAG Interface

    341
  • 28.6 In-Circuit Serial Programming

    341
  • 28.7 In-Circuit Debugger

    341
  • 28.8 Code Protection and CodeGuard Security

    341
    • TABLE 28-3: CODE FLASH SECURITY Segment SIZES FOR 32 KB Devices

      342
    • TABLE 28-4: CODE FLASH SECURITY Segment SIZES FOR 64 KB Devices

      343
    • TABLE 28-5: CODE FLASH SECURITY Segment SIZES FOR 128 KB Devices

      344
• 29.0 Instruction Set Summary

  345
  • TABLE 29-1: Symbols used in Opcode Descriptions (Continued)

    346
  • TABLE 29-2: Instruction Set OVERVIEW (Continued)

    348
• 30.0 Development Support

  353
  • 30.1 MPLAB Integrated Development Environment Software

    353
  • 30.2 MPLAB C Compilers for Various Device Families

    354
  • 30.3 HI-TECH C for Various Device Families

    354
  • 30.4 MPASM Assembler

    354
  • 30.5 MPLINK Object Linker/ MPLIB Object Librarian

    354
  • 30.6 MPLAB Assembler, Linker and Librarian for Various Device Families

    354
  • 30.7 MPLAB SIM Software Simulator

    355
  • 30.8 MPLAB REAL ICE In-Circuit Emulator System

    355
  • 30.9 MPLAB ICD 3 In-Circuit Debugger System

    355
  • 30.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express

    355
  • 30.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express

    356
  • 30.12 MPLAB PM3 Device Programmer

    356
  • 30.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits

    356
• 31.0 Electrical Characteristics

  357
  • Absolute Maximum Ratings(1)

    357
  • 31.1 DC Characteristics

    358
    • TABLE 31-1: Operating MIPS vs. Voltage

      358
    • TABLE 31-2: Thermal Operating Conditions

      358
    • TABLE 31-3: Thermal Packaging Characteristics

      358
    • TABLE 31-4: DC Temperature and Voltage specifications

      359
    • TABLE 31-5: DC Characteristics: Operating Current (Idd)

      360
    • TABLE 31-6: DC Characteristics: Idle Current (iidle)

      361
    • TABLE 31-7: DC Characteristics: Power-Down Current (Ipd)

      362
    • TABLE 31-8: DC Characteristics: doze Current (Idoze)

      363
    • TABLE 31-9: DC Characteristics: I/O Pin Input Specifications (Continued)

      364
    • TABLE 31-10: DC Characteristics: I/O Pin Output Specifications

      367
    • TABLE 31-11: Electrical Characteristics: BOR

      368
    • TABLE 31-12: DC Characteristics: Program Memory

      368
    • TABLE 31-13: Internal Voltage Regulator Specifications

      368
  • 31.2 AC Characteristics and Timing Parameters

    369
    • TABLE 31-14: Temperature and Voltage Specifications – AC

      369
    • FIGURE 31-1: Load Conditions for Device Timing Specifications

      369
    • TABLE 31-15: cAPAcITIVE lOADING rEQUIREMENTS ON oUTPUT pINS

      369
    • FIGURE 31-2: External Clock Timing

      370
    • TABLE 31-16: External Clock Timing Requirements

      370
    • TABLE 31-17: PLL Clock Timing Specifications (Vdd = 3.0V to 3.6V)

      371
    • TABLE 31-18: AC Characteristics: Internal RC Accuracy

      371
    • TABLE 31-19: Internal RC accuracy

      371
    • FIGURE 31-3: I/O Timing Characteristics

      372
    • TABLE 31-20: I/O Timing Requirements

      372
    • FIGURE 31-4: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Characteristics

      373
    • TABLE 31-21: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer Timing Requirements

      374
    • FIGURE 31-5: Timer1, 2 and 3 External Clock Timing Characteristics

      375
    • TABLE 31-22: Timer1 External Clock Timing Requirements(1)

      375
    • TABLE 31-23: Timer2 and Timer4 External Clock Timing Requirements

      376
    • TABLE 31-24: Timer3 and Timer5 External Clock Timing Requirements

      376
    • FIGURE 31-6: TimerQ (QEI Module) External Clock Timing Characteristics

      377
    • TABLE 31-25: QEI module External Clock Timing Requirements

      377
    • FIGURE 31-7: INPUT CAPTURE (CAPx) TIMING Characteristics

      378
    • TABLE 31-26: Input Capture timing requirements

      378
    • FIGURE 31-8: Output Compare Module (OCx) Timing Characteristics

      378
    • TABLE 31-27: Output Compare Module timing requirements

      378
    • FIGURE 31-9: OC/PWM Module Timing Characteristics

      379
    • TABLE 31-28: Simple OC/PWM MODE Timing Requirements

      379
    • FIGURE 31-10: Motor Control PWM Module fault Timing Characteristics

      380
    • FIGURE 31-11: Motor Control PWM Module Timing Characteristics

      380
    • TABLE 31-29: Motor Control PWM Module Timing Requirements

      380
    • FIGURE 31-12: QEA/QEB Input Characteristics

      381
    • TABLE 31-30: Quadrature Decoder Timing Requirements

      381
    • FIGURE 31-13: QEI Module Index Pulse Timing Characteristics

      382
    • TABLE 31-31: QEI INDEX PULSE Timing Requirements

      382
    • TABLE 31-32: SPIx Maximum Data/CLock Rate Summary

      383
    • FIGURE 31-14: SPIx MASTER MODE (Half-Duplex, Transmit Only CKE = 0) TIMING CHARACTERISTICS

      383
    • FIGURE 31-15: SPIx MASTER MODE (Half-Duplex, Transmit Only CKE = 1) TIMING CHARACTERISTICS

      383
    • TABLE 31-33: SPIx Master Mode (Half-Duplex, Transmit Only) Timing Requirements

      384
    • FIGURE 31-16: SPIx MASTER MODE (Full-Duplex, CKE = 1, CKP = X, SMP = 1) TIMING CHARACTERISTICS

      385
    • TABLE 31-34: SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Requirements

      385
    • FIGURE 31-17: SPIx MASTER MODE (Full-Duplex, CKE = 0, CKP = X, SMP = 1) TIMING CHARACTERISTICS

      386
    • TABLE 31-35: SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements

      386
    • FIGURE 31-18: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS

      387
    • TABLE 31-36: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Timing Requirements

      388
    • FIGURE 31-19: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS

      389
    • TABLE 31-37: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Timing Requirements

      390
    • FIGURE 31-20: SPIx SLAVE MODE (Full-Duplex CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS

      391
    • TABLE 31-38: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Timing Requirements

      392
    • FIGURE 31-21: SPIx SLAVE MODE (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS

      393
    • TABLE 31-39: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Timing Requirements

      394
    • FIGURE 31-22: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)

      395
    • FIGURE 31-23: I2Cx Bus Data Timing Characteristics (Master mode)

      395
    • TABLE 31-40: I2Cx Bus Data Timing Requirements (Master Mode)

      396
    • FIGURE 31-24: I2Cx Bus Start/Stop Bits Timing Characteristics (slave mode)

      397
    • FIGURE 31-25: I2Cx Bus Data Timing Characteristics (slave mode)

      397
    • TABLE 31-41: I2Cx Bus Data Timing Requirements (Slave Mode)

      398
    • FIGURE 31-26: ECAN Module I/O Timing Characteristics

      399
    • TABLE 31-42: ECAN Module I/O Timing Requirements

      399
    • TABLE 31-43: ADC Module Specifications

      400
    • TABLE 31-44: ADC Module Specifications (12-bit Mode)

      401
    • TABLE 31-45: ADC Module Specifications (10-bit Mode)

      402
    • FIGURE 31-27: ADC Conversion (12-bit mode) Timing Characteristics (asam = 0, ssrc<2:0> = 000)

      403
    • TABLE 31-46: ADC Conversion (12-bit Mode) TiminG rEQUIREMENTS

      404
    • FIGURE 31-28: ADC Conversion (10-bit mode) Timing Characteristics (chps<1:0> = 01, SIMSAM = 0, asam = 0, ssrc<2:0> = 000)

      405
    • FIGURE 31-29: ADC Conversion (10-bit mode) Timing cHARACTERISTICS (chps<1:0> = 01, SIMSAM = 0, asam = 1, ssrc<2:0> = 111, SAMC<4:0> = 00001)

      405
    • TABLE 31-47: ADC CONVERSION (10-bit mode) TIMING rEQUIREMENTS

      406
    • TABLE 31-48: Audio DAC Module Specifications

      406
    • TABLE 31-49: Comparator Timing Specifications

      407
    • TABLE 31-50: Comparator Module Specifications

      407
    • TABLE 31-51: Comparator Reference Voltage Settling Time Specifications

      408
    • TABLE 31-52: Comparator Reference Voltage Specifications

      408
    • FIGURE 31-30: Parallel Slave Port Timing Diagram

      408
    • TABLE 31-53: Setting Time Specifications

      409
    • FIGURE 31-31: Parallel Master Port Read Timing DiAgram

      409
    • TABLE 31-54: Parallel Master Port Read Timing Requirements

      410
    • FIGURE 31-32: Parallel Master Port Write Timing Diagram

      410
    • TABLE 31-55: Parallel Master Port Write Timing Requirements

      411
    • TABLE 31-56: DMA READ/Write Timing Requirements

      411
• 32.0 High Temperature Electrical Characteristics

  413
  • Absolute Maximum Ratings(1)

    413
  • 32.1 High Temperature DC Characteristics

    414
    • TABLE 32-1: Operating MIPS vs. Voltage

      414
    • TABLE 32-2: Thermal Operating Conditions

      414
    • TABLE 32-3: DC Temperature and Voltage Specifications

      414
    • TABLE 32-4: DC Characteristics: Power-down Current (Ipd)

      415
    • TABLE 32-5: DC Characteristics: Doze Current (Idoze)

      415
    • TABLE 32-6: DC Characteristics: I/O Pin Output Specifications

      416
    • TABLE 32-7: DC Characteristics: Program Memory

      417
  • 32.2 AC Characteristics and Timing Parameters

    418
    • TABLE 32-8: Temperature and Voltage Specifications – AC

      418
    • FIGURE 32-1: Load Conditions for Device Timing Specifications

      418
    • TABLE 32-9: PLL Clock Timing Specifications

      418
    • TABLE 32-10: SPIx Master Mode (cke = 0) Timing Requirements

      419
    • TABLE 32-11: SPIx Module Master Mode (cke = 1) Timing Requirements

      419
    • TABLE 32-12: SPIx Module Slave Mode (cke = 0) Timing Requirements

      420
    • TABLE 32-13: SPIx Module Slave Mode (cke = 1) Timing Requirements

      420
    • TABLE 32-14: ADC Module Specifications

      421
    • TABLE 32-15: ADC Module Specifications (12-bit Mode)

      421
    • TABLE 32-16: ADC Module Specifications (10-bit Mode)

      422
    • TABLE 32-17: ADC Conversion (12-bit Mode) Timing Requirements

      423
    • TABLE 32-18: ADC Conversion (10-bit mode) Timing Requirements

      423
• 32.0 DC and AC Device Characteristics Graphs

  425
  • FIGURE 32-1: Voh – 2x Driver Pins

    425
  • FIGURE 32-2: Voh – 4x Driver Pins

    425
  • FIGURE 32-3: Voh – 8x Driver Pins

    425
  • FIGURE 32-4: Voh – 16x Driver Pins

    425
  • FIGURE 32-5: Vol – 2x Driver Pins

    426
  • FIGURE 32-6: Vol – 4x Driver Pins

    426
  • FIGURE 32-7: Vol – 8x Driver Pins

    426
  • FIGURE 32-8: Vol – 16x Driver Pins

    426
  • FIGURE 32-9: Typical Ipd Current @ Vdd = 3.3V, +85ºC

    427
  • FIGURE 32-10: Typical Idd Current @ Vdd = 3.3V, +85ºC

    427
  • FIGURE 32-11: Typical Idoze Current @ Vdd = 3.3V, +85ºC

    427
  • FIGURE 32-12: Typical Iidle Current @ Vdd = 3.3V, +85ºC

    427
  • FIGURE 32-13: Typical FRC Frequency @ Vdd = 3.3V

    428
  • FIGURE 32-14: Typical LPRC Frequency @ Vdd = 3.3V

    428
• 33.0 Packaging Information

  429
  • 33.1 Package Details

    430
• Appendix A: Revision History

  439
  • Revision A (August 2007)

    439
  • Revision B (March 2008)

    439
    • TABLE A-1: Major Section Updates (Continued)

      439
  • Revision C (May 2009)

    441
    • TABLE A-2: Major Section Updates (Continued)

      441
  • Revision D (November 2009)

    444
    • TABLE A-3: Major Section Updates

      444
  • Revision E (January 2011)

    445
    • TABLE A-4: Major Section Updates (Continued)

      445
  • Revision F (August 2011)

    448
    • TABLE A-5: Major Section Updates

      448
  • Revision G (April 2012)

    448
    • TABLE A-6: Major Section Updates

      448
• INDEX

  449
• The Microchip Web Site

  455
• Customer Change Notification Service

  455
• Customer Support

  455
• Reader Response

  456
• Product Identification System

  457