用户手册 — Motorola MC68HC05RC16

目录

• List of Sections

  3
• Table of Contents

  5
• List of Figures

  11
• List of Tables

  13
• Section 1. General Description

  15
  • 1.1 Contents

    15
  • 1.2 Introduction

    16
  • 1.3 Features

    16
  • 1.4 Mask Options

    19
  • 1.5 Signal Description

    21
    • 1.5.1 VDD and VSS

      23
    • 1.5.2 IRQ (Maskable Interrupt Request)

      23
    • 1.5.3 OSC1 and OSC2

      24
    • 1.5.4 RESET

      25
    • 1.5.5 LPRST

      25
    • 1.5.6 IRO

      25
    • 1.5.7 PA0–PA7

      25
    • 1.5.8 PB0–PB7

      25
    • 1.5.9 PC0–PC3 (PC4–PC7)

      26
• Section 2. Memory

  27
  • 2.1 Contents

    27
  • 2.2 Introduction

    27
  • 2.3 Memory Map

    27
    • 2.3.1 ROM

      30
    • 2.3.2 ROM Security

      30
    • 2.3.3 RAM

      31
  • 2.4 Input/Output Programming

    31
• Section 3. Central Processor Unit

  33
  • 3.1 Contents

    33
  • 3.2 Introduction

    33
  • 3.3 Accumulator

    34
  • 3.4 Index Register

    34
  • 3.5 Condition Code Register

    35
  • 3.6 Stack Pointer

    36
  • 3.7 Program Counter

    36
• Section 4. Interrupts

  37
  • 4.1 Contents

    37
  • 4.2 Introduction

    37
  • 4.3 CPU Interrupt Processing

    38
  • 4.4 Reset Interrupt Sequence

    39
  • 4.5 Software Interrupt (SWI)

    39
  • 4.6 Hardware Interrupts

    41
  • 4.7 External Interrupt (IRQ/Port B Keyscan)

    41
  • 4.8 External Interrupt Timing

    42
  • 4.9 Carrier Modulator Transmitter Interrupt (CMT)

    42
  • 4.10 Core Timer Interrupt

    43
• Section 5. Resets

  45
  • 5.1 Contents

    45
  • 5.2 Introduction

    45
  • 5.3 External Reset (RESET)

    46
  • 5.4 Low-Power External Reset (LPRST)

    48
  • 5.5 Internal Resets

    48
    • 5.5.1 Power-On Reset (POR)

      48
    • 5.5.2 Computer Operating Properly Reset (COPR)

      49
      • 5.5.2.1 Resetting the COP

        49
      • 5.5.2.2 COP During Wait Mode

        49
      • 5.5.2.3 COP During Stop Mode

        49
      • 5.5.2.4 COP Watchdog Timer Considerations

        50
      • 5.5.2.5 COP Register

        51
    • 5.5.3 Illegal Address

      51
• Section 6. Low-Power Modes

  53
  • 6.1 Contents

    53
  • 6.2 Introduction

    53
  • 6.3 Stop Mode

    53
  • 6.4 Stop Recovery

    54
  • 6.5 Wait Mode

    54
  • 6.6 Low-Power Reset

    55
• Section 7. Parallel Input/Output (I/O)

  57
  • 7.1 Contents

    57
  • 7.2 Introduction

    57
  • 7.3 Port A

    57
  • 7.4 Port B

    58
  • 7.5 Port C

    58
  • 7.6 Input/Output Programming

    59
• Section 8. Core Timer

  61
  • 8.1 Contents

    61
  • 8.2 Introduction

    61
  • 8.3 Core Timer Control and Status Register

    63
  • 8.4 Core Timer Counter Register

    65
  • 8.5 Computer Operating Properly (COP) Reset

    66
  • 8.6 Timer During Wait Mode

    66
• Section 9. Carrier Modulator Transmitter (CMT)

  67
  • 9.1 Contents

    67
  • 9.2 Introduction

    67
  • 9.3 Overview

    68
  • 9.4 Carrier Generator

    70
    • 9.4.1 Time Counter

      71
    • 9.4.2 Carrier Generator Data Registers (CHR1, CLR1...

      72
  • 9.5 Modulator

    74
    • 9.5.1 Time Mode

      76
    • 9.5.2 FSK Mode

      77
    • 9.5.3 Extended Space Operation

      78
      • 9.5.3.1 End Of Cycle (EOC) Interrupt

        79
      • 9.5.3.2 Modulator Control and Status Register

        80
    • 9.5.4 Modulator Period Data Registers (MDR1, MDR2,...

      83
• Section 10. Instruction Set

  85
  • 10.1 Contents

    85
  • 10.2 Introduction

    86
  • 10.3 Addressing Modes

    86
    • 10.3.1 Inherent

      87
    • 10.3.2 Immediate

      87
    • 10.3.3 Direct

      87
    • 10.3.4 Extended

      87
    • 10.3.5 Indexed, No Offset

      88
    • 10.3.6 Indexed, 8Bit Offset

      88
    • 10.3.7 Indexed,16Bit Offset

      88
    • 10.3.8 Relative

      89
  • 10.4 Instruction Types

    89
    • 10.4.1 Register/Memory Instructions

      90
    • 10.4.2 Read-Modify-Write Instructions

      91
    • 10.4.3 Jump/Branch Instructions

      92
    • 10.4.4 Bit Manipulation Instructions

      94
    • 10.4.5 Control Instructions

      95
  • 10.5 Instruction Set Summary

    96
  • OpcodeMap

    102
• Section 11. Electrical Specifications

  103
  • 11.1 Contents

    103
  • 11.2 Introduction

    103
  • 11.3 Maximum Ratings

    104
  • 11.4 Operating Range

    105
  • 11.5 Thermal Characteristics

    105
  • 11.6 DC Electrical Characteristics (5.0 Vdc)

    106
  • 11.7 DC Electrical Characteristics (2.2 Vdc)

    107
  • 11.8 Control Timing (5.0 Vdc and 2.2 Vdc)

    109
• Section 12. Mechanical Specifications

  111
  • 12.1 Contents

    111
  • 12.2 Introduction

    111
  • 12.3 28-Pin Plastic Dual In-Line Package (Case 710...

    112
  • 12.4 28-Pin Small Outline Integrated Circuit Packa...

    112
  • 12.5 44-Pin Plastic Leaded Chip Carrier Package (C...

    113
• Section 13. Ordering Information

  115
  • 13.1 Contents

    115
  • 13.2 Introduction

    115
  • 13.3 MCU Ordering Forms

    115
  • 13.4 Application Program Media

    116
  • 13.5 ROM Program Verification

    117
  • 13.6 ROM Verification Units (RVUs)

    118
  • 13.7 MC Order Numbers

    118
• Appendix A. MC68HC05RC8

  119
  • A.1 Contents

    119
  • A.2 Introduction

    119
  • A.3 Memory Map

    119