用户手册目录Revision History2Table of Contents3List of Figures9List of Tables11Preface15Table 0-1 List of MC9S12C and MC9S12GC Family members15Table 0-2 MC9S12C-Family Package Option Summary15Figure 0-1 Order Part number Coding16Table 0-3 MC9S12C-Family Part Number Coding16Table 0-4 MC9S12GC-Family Part Number Coding19Table 0-5 Document References21Terminology21Section 1 Introduction231.1 Overview231.2 Features231.3 Modes of Operation251.4 Block Diagram27Figure 1-1 MC9S12C-Family Block Diagram271.5 Device Memory Map28Table 1-1 Device Register Map Overview28Figure 1-2 MC9S12C128 and MC9S12GC128 User configurable Memory Map29Figure 1-3 MC9S12C96 User Configurable Memory Map30Figure 1-4 MC9S12C64 and MC9S12GC64 User Configurable Memory Map31Figure 1-5 MC9S12C32 and MC9S12GC32 User Configurable Memory Map32Figure 1-6 MC9S12GC16 User Configurable Memory Map331.6 Detailed Register Map33$0000 - $000F MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface)34$0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control)34$0015 - $0016 INT map 1 of 2 (HCS12 Interrupt)35$0017 - $0017 MMC map 2 of 4 (HCS12 Module Mapping Control)35$0018 - $0018 Miscellaneous Peripherals (Device User Guide)35$0019 - $0019 VREG3V3 (Voltage Regulator)35$001A - $001B Miscellaneous Peripherals (Device User Guide)35$001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control,36Device User Guide)36$001E - $001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface)36$001F - $001F INT map 2 of 2 (HCS12 Interrupt)36$0020 - $002F DBG (including BKP) map 1 of 1 (HCS12 Debug)36$0030 - $0031 MMC map 4 of 4 (HCS12 Module Mapping Control)37$0032 - $0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface)37$0034 - $003F CRG (Clock and Reset Generator)37$0040 - $006F TIM (Timer 16 Bit 8 Channels)38$0070 - $007F Reserved40$0080 - $009F ATD (Analog to Digital Converter 10 Bit 8 Channel)40$00A0 - $00C7 Reserved41$00C8 - $00CF SCI (Asynchronous Serial Interface)42$00D0 - $00D7 Reserved42$00D8 - $00DF SPI (Serial Peripheral Interface)42$00E0 - $00FF PWM (Pulse Width Modulator)43$0100 - $010F Flash Control Register44$0110 - $013F Reserved45$0140 - $017F CAN (Motorola Scalable CAN - MSCAN)45Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout46$0180 - $023F Reserved47$0240 - $027F PIM (Port Interface Module)47$0280 - $03FF Reserved space501.7 Part ID Assignments50Table 1-3 Assigned Part ID Numbers50Table 1-4 Memory size registers50Section 2 Signal Description522.1 Device Pinout52Figure 2-1 Pin Assignments in 80 QFP for MC9S12C-Family52Figure 2-2 Pin assignments in 52 LQFP for MC9S12C-Family53Figure 2-3 Pin Assignments in 48 LQFP for MC9S12C-Family542.2 Signal Properties Summary55Table 2-1 Signal Properties552.3 Detailed Signal Descriptions57Figure 2-4 PLL Loop Filter Connections57Figure 2-5 Colpitts Oscillator Connections (PE7=1)59Figure 2-6 Pierce Oscillator Connections (PE7=0)59Figure 2-7 External Clock Connections (PE7=0)592.4 Power Supply Pins63Table 2-2 MC9S12C-Family Power and Ground Connection Summary64Section 3 System Clock Description64Figure 3-1 Clock Connections65Section 4 Modes of Operation654.1 Overview654.2 Chip Configuration Summary65Table 4-1 Mode Selection66Table 4-2 Clock Selection Based on PE7664.3 Security664.4 Low Power Modes67Section 5 Resets and Interrupts685.1 Overview685.2 Vectors68Table 5-1 Interrupt Vector Locations685.3 Resets69Table 5-2 Reset Summary70Section 6 HCS12 Core Block Description706.1 Device-specific information70Table 6-1 Device Specific Flash PAGE Mapping71Section 7 Voltage Regulator (VREG) Block Description727.1 Device-specific information72Section 8 Recommended Printed Circuit Board Layout72Table 8-1 Recommended External Component Values73Figure 8-1 Recommended PCB Layout (48 LQFP)74Figure 8-2 Recommended PCB Layout (52 LQFP)75Figure 8-3 Recommended PCB Layout (80 QFP)76Figure 8-4 Recommended PCB Layout for 48 LQFP Pierce Oscillator77Figure 8-5 Recommended PCB Layout for 52 LQFP Pierce Oscillator78Figure 8-6 Recommended PCB Layout for 80QFP Pierce Oscillator79Section 9 Clock Reset Generator (CRG) Block Description799.1 Device-specific information79Section 10 Oscillator (OSC) Block Description80Section 11 Timer (TIM) Block Description80Section 12 Analog to Digital Converter (ATD) Block Description8012.1 Device-specific information80Section 13 Serial Communications Interface (SCI) Block Description80Section 14 Serial Peripheral Interface (SPI) Block Description80Section 15 Flash Block Description81Section 16 RAM Block Description81Section 17 Pulse Width Modulator (PWM) Block Description81Section 18 MSCAN Block Description81Section 19 Port Integration Module (PIM) Block Description81Appendix A Electrical Characteristics83A.1 General83Table A-1 Absolute Maximum Ratings85Table A-2 ESD and Latch-up Test Conditions86Table A-3 ESD and Latch-Up Protection Characteristics86Table A-4 Operating Conditions87Table A-5 Thermal Package Characteristics89Table A-6 5V I/O Characteristics90Table A-7 3.3V I/O Characteristics91Table A-8 Supply Current Characteristics for MC9S12C3293Table A-9 Supply Current Characteristics for MC9S12C64,MC9S12C96,MC9S12C12894Appendix B Electrical Specifications95B.1 Voltage Regulator Operating Conditions95Table B-1 Voltage Regulator Electrical Parameters95B.2 Chip Power-up and LVI/LVR graphical explanation96Figure B-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled)96B.3 Output Loads96Table B-2 Voltage Regulator - Capacitive Loads97B.4 ATD Characteristics99Table B-3 ATD Operating Characteristics99Table B-4 ATD Operating Characteristics100Table B-5 ATD Electrical Characteristics101Table B-6 ATD Conversion Performance102Table B-7 ATD Conversion Performance102Figure B-2 ATD Accuracy Definitions104B.5 NVM, Flash and EEPROM105Table B-8 NVM Timing Characteristics106Table B-9 NVM Reliability Characteristics107B.6 Reset, Oscillator and PLL109Table B-10 Startup Characteristics109Table B-11 Oscillator Characteristics111Figure B-3 Basic PLL functional diagram112Figure B-4 Jitter Definitions114Figure B-5 Maximum bus clock jitter approximation114Table B-12 PLL Characteristics115B.7 MSCAN117Table B-13 MSCAN Wake-up Pulse Characteristics117B.8 SPI119Appendix C Electrical Specifications119Table C-1 Measurement Conditions119C.1 Master Mode119Figure C-1 SPI Master Timing (CPHA=0)119Figure C-2 SPI Master Timing (CPHA=1)120Table C-2 SPI Master Mode Timing Characteristics120C.2 Slave Mode121Figure C-3 SPI Slave Timing (CPHA=0)121Figure C-4 SPI Slave Timing (CPHA=1)122Table C-3 SPI Slave Mode Timing Characteristics122C.3 External Bus Timing123Figure C-5 General External Bus Timing123Table C-4 Expanded Bus Timing Characteristics (5V Range)124Table C-5 Expanded Bus Timing Characteristics (3.3V Range)125Appendix D Package Information127D.1 General127D.2 80-pin QFP package128Figure D-1 80-pin QFP Mechanical Dimensions (case no. 841B)128D.3 52-pin LQFP package129Figure D-2 52-pin LQFP Mechanical Dimensions (case no. 848D-03)129D.4 48-pin LQFP package130Figure D-3 48-pin LQFP Mechanical Dimensions (case no.932-03 ISSUE F)130Appendix E Emulation Information131E.1 General131Figure 19-1 Pin Assignments in 112-pin LQFP131E.2 112-pin LQFP package133Figure 19-2 112-pin LQFP mechanical dimensions (case no. 987)80-pin QFP Mechanical Dimensions (ca...133Device User Guide End Sheet135文件大小: 2.0 MB页数: 136Language: English打开用户手册