用户手册 — Motorola MC9S12GC-Family

目录

• Revision History

  2
• Table of Contents

  3
• List of Figures

  9
• List of Tables

  11
• Preface

  15
  • Table 0-1 List of MC9S12C and MC9S12GC Family members

    15
  • Table 0-2 MC9S12C-Family Package Option Summary

    15
  • Figure 0-1 Order Part number Coding

    16
  • Table 0-3 MC9S12C-Family Part Number Coding

    16
  • Table 0-4 MC9S12GC-Family Part Number Coding

    19
  • Table 0-5 Document References

    21
    • Terminology

      21
• Section 1 Introduction

  23
  • 1.1 Overview

    23
  • 1.2 Features

    23
  • 1.3 Modes of Operation

    25
  • 1.4 Block Diagram

    27
    • Figure 1-1 MC9S12C-Family Block Diagram

      27
  • 1.5 Device Memory Map

    28
    • Table 1-1 Device Register Map Overview

      28
    • Figure 1-2 MC9S12C128 and MC9S12GC128 User configurable Memory Map

      29
    • Figure 1-3 MC9S12C96 User Configurable Memory Map

      30
    • Figure 1-4 MC9S12C64 and MC9S12GC64 User Configurable Memory Map

      31
    • Figure 1-5 MC9S12C32 and MC9S12GC32 User Configurable Memory Map

      32
    • Figure 1-6 MC9S12GC16 User Configurable Memory Map

      33
  • 1.6 Detailed Register Map

    33
    • $0000 - $000F MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface)

      34
    • $0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control)

      34
    • $0015 - $0016 INT map 1 of 2 (HCS12 Interrupt)

      35
    • $0017 - $0017 MMC map 2 of 4 (HCS12 Module Mapping Control)

      35
    • $0018 - $0018 Miscellaneous Peripherals (Device User Guide)

      35
    • $0019 - $0019 VREG3V3 (Voltage Regulator)

      35
    • $001A - $001B Miscellaneous Peripherals (Device User Guide)

      35
    • $001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control,

      36
    • Device User Guide)

      36
    • $001E - $001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface)

      36
    • $001F - $001F INT map 2 of 2 (HCS12 Interrupt)

      36
    • $0020 - $002F DBG (including BKP) map 1 of 1 (HCS12 Debug)

      36
    • $0030 - $0031 MMC map 4 of 4 (HCS12 Module Mapping Control)

      37
    • $0032 - $0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface)

      37
    • $0034 - $003F CRG (Clock and Reset Generator)

      37
    • $0040 - $006F TIM (Timer 16 Bit 8 Channels)

      38
    • $0070 - $007F Reserved

      40
    • $0080 - $009F ATD (Analog to Digital Converter 10 Bit 8 Channel)

      40
    • $00A0 - $00C7 Reserved

      41
    • $00C8 - $00CF SCI (Asynchronous Serial Interface)

      42
    • $00D0 - $00D7 Reserved

      42
    • $00D8 - $00DF SPI (Serial Peripheral Interface)

      42
    • $00E0 - $00FF PWM (Pulse Width Modulator)

      43
    • $0100 - $010F Flash Control Register

      44
    • $0110 - $013F Reserved

      45
    • $0140 - $017F CAN (Motorola Scalable CAN - MSCAN)

      45
    • Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout

      46
    • $0180 - $023F Reserved

      47
    • $0240 - $027F PIM (Port Interface Module)

      47
    • $0280 - $03FF Reserved space

      50
  • 1.7 Part ID Assignments

    50
    • Table 1-3 Assigned Part ID Numbers

      50
    • Table 1-4 Memory size registers

      50
• Section 2 Signal Description

  52
  • 2.1 Device Pinout

    52
    • Figure 2-1 Pin Assignments in 80 QFP for MC9S12C-Family

      52
    • Figure 2-2 Pin assignments in 52 LQFP for MC9S12C-Family

      53
    • Figure 2-3 Pin Assignments in 48 LQFP for MC9S12C-Family

      54
  • 2.2 Signal Properties Summary

    55
    • Table 2-1 Signal Properties

      55
  • 2.3 Detailed Signal Descriptions

    57
    • Figure 2-4 PLL Loop Filter Connections

      57
    • Figure 2-5 Colpitts Oscillator Connections (PE7=1)

      59
    • Figure 2-6 Pierce Oscillator Connections (PE7=0)

      59
    • Figure 2-7 External Clock Connections (PE7=0)

      59
  • 2.4 Power Supply Pins

    63
    • Table 2-2 MC9S12C-Family Power and Ground Connection Summary

      64
• Section 3 System Clock Description

  64
  • Figure 3-1 Clock Connections

    65
• Section 4 Modes of Operation

  65
  • 4.1 Overview

    65
  • 4.2 Chip Configuration Summary

    65
    • Table 4-1 Mode Selection

      66
    • Table 4-2 Clock Selection Based on PE7

      66
  • 4.3 Security

    66
  • 4.4 Low Power Modes

    67
• Section 5 Resets and Interrupts

  68
  • 5.1 Overview

    68
  • 5.2 Vectors

    68
    • Table 5-1 Interrupt Vector Locations

      68
  • 5.3 Resets

    69
    • Table 5-2 Reset Summary

      70
• Section 6 HCS12 Core Block Description

  70
  • 6.1 Device-specific information

    70
    • Table 6-1 Device Specific Flash PAGE Mapping

      71
• Section 7 Voltage Regulator (VREG) Block Description

  72
  • 7.1 Device-specific information

    72
• Section 8 Recommended Printed Circuit Board Layout

  72
  • Table 8-1 Recommended External Component Values

    73
  • Figure 8-1 Recommended PCB Layout (48 LQFP)

    74
  • Figure 8-2 Recommended PCB Layout (52 LQFP)

    75
  • Figure 8-3 Recommended PCB Layout (80 QFP)

    76
  • Figure 8-4 Recommended PCB Layout for 48 LQFP Pierce Oscillator

    77
  • Figure 8-5 Recommended PCB Layout for 52 LQFP Pierce Oscillator

    78
  • Figure 8-6 Recommended PCB Layout for 80QFP Pierce Oscillator

    79
• Section 9 Clock Reset Generator (CRG) Block Description

  79
  • 9.1 Device-specific information

    79
• Section 10 Oscillator (OSC) Block Description

  80
• Section 11 Timer (TIM) Block Description

  80
• Section 12 Analog to Digital Converter (ATD) Block Description

  80
  • 12.1 Device-specific information

    80
• Section 13 Serial Communications Interface (SCI) Block Description

  80
• Section 14 Serial Peripheral Interface (SPI) Block Description

  80
• Section 15 Flash Block Description

  81
• Section 16 RAM Block Description

  81
• Section 17 Pulse Width Modulator (PWM) Block Description

  81
• Section 18 MSCAN Block Description

  81
• Section 19 Port Integration Module (PIM) Block Description

  81
• Appendix A Electrical Characteristics

  83
  • A.1 General

    83
    • Table A-1 Absolute Maximum Ratings

      85
    • Table A-2 ESD and Latch-up Test Conditions

      86
    • Table A-3 ESD and Latch-Up Protection Characteristics

      86
    • Table A-4 Operating Conditions

      87
    • Table A-5 Thermal Package Characteristics

      89
    • Table A-6 5V I/O Characteristics

      90
    • Table A-7 3.3V I/O Characteristics

      91
    • Table A-8 Supply Current Characteristics for MC9S12C32

      93
    • Table A-9 Supply Current Characteristics for MC9S12C64,MC9S12C96,MC9S12C128

      94
• Appendix B Electrical Specifications

  95
  • B.1 Voltage Regulator Operating Conditions

    95
    • Table B-1 Voltage Regulator Electrical Parameters

      95
  • B.2 Chip Power-up and LVI/LVR graphical explanation

    96
    • Figure B-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled)

      96
  • B.3 Output Loads

    96
    • Table B-2 Voltage Regulator - Capacitive Loads

      97
  • B.4 ATD Characteristics

    99
    • Table B-3 ATD Operating Characteristics

      99
    • Table B-4 ATD Operating Characteristics

      100
    • Table B-5 ATD Electrical Characteristics

      101
    • Table B-6 ATD Conversion Performance

      102
    • Table B-7 ATD Conversion Performance

      102
    • Figure B-2 ATD Accuracy Definitions

      104
  • B.5 NVM, Flash and EEPROM

    105
    • Table B-8 NVM Timing Characteristics

      106
    • Table B-9 NVM Reliability Characteristics

      107
  • B.6 Reset, Oscillator and PLL

    109
    • Table B-10 Startup Characteristics

      109
    • Table B-11 Oscillator Characteristics

      111
    • Figure B-3 Basic PLL functional diagram

      112
    • Figure B-4 Jitter Definitions

      114
    • Figure B-5 Maximum bus clock jitter approximation

      114
    • Table B-12 PLL Characteristics

      115
  • B.7 MSCAN

    117
    • Table B-13 MSCAN Wake-up Pulse Characteristics

      117
  • B.8 SPI

    119
• Appendix C Electrical Specifications

  119
  • Table C-1 Measurement Conditions

    119
  • C.1 Master Mode

    119
    • Figure C-1 SPI Master Timing (CPHA=0)

      119
    • Figure C-2 SPI Master Timing (CPHA=1)

      120
    • Table C-2 SPI Master Mode Timing Characteristics

      120
  • C.2 Slave Mode

    121
    • Figure C-3 SPI Slave Timing (CPHA=0)

      121
    • Figure C-4 SPI Slave Timing (CPHA=1)

      122
    • Table C-3 SPI Slave Mode Timing Characteristics

      122
  • C.3 External Bus Timing

    123
    • Figure C-5 General External Bus Timing

      123
    • Table C-4 Expanded Bus Timing Characteristics (5V Range)

      124
    • Table C-5 Expanded Bus Timing Characteristics (3.3V Range)

      125
• Appendix D Package Information

  127
  • D.1 General

    127
  • D.2 80-pin QFP package

    128
    • Figure D-1 80-pin QFP Mechanical Dimensions (case no. 841B)

      128
  • D.3 52-pin LQFP package

    129
    • Figure D-2 52-pin LQFP Mechanical Dimensions (case no. 848D-03)

      129
  • D.4 48-pin LQFP package

    130
    • Figure D-3 48-pin LQFP Mechanical Dimensions (case no.932-03 ISSUE F)

      130
• Appendix E Emulation Information

  131
  • E.1 General

    131
    • Figure 19-1 Pin Assignments in 112-pin LQFP

      131
  • E.2 112-pin LQFP package

    133
    • Figure 19-2 112-pin LQFP mechanical dimensions (case no. 987)80-pin QFP Mechanical Dimensions (ca...

      133
• Device User Guide End Sheet

  135