用户手册目录SPRS292A - TMS320C6711D1features1Table of Contents2REVISION HISTORY3GDP and ZDP BGA packages (bottom view)4description5device characteristics6device compatibility7functional block and CPU (DSP core) diagram8CPU (DSP core) description9memory map summary11peripheral register descriptions12signal groups description17DEVICE CONFIGURATIONS20device configurations at device reset20DEVCFG register description22TERMINAL FUNCTIONS23Terminal Functions24development support36Software Development Tools:36Hardware Development Tools:36device support37device and development-support tool nomenclature37TMX37TMP37TMS37TMDX37TMDS37documentation support39CPU CSR register description40cache configuration (CCFG) register description42interrupt sources and interrupt selector43EDMA module and EDMA selector44ESEL0 Register (0x01A0 FF00)45ESEL1 Register (0x01A0 FF04)45ESEL3 Register (0x01A0 FF0C)45PLL and PLL controller46PLLCSR Register (0x01B7 C100)49PLLM Register (0x01B7 C110)50PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 Registers51OSCDIV1 Register (0x01B7 C124)52general-purpose input/output (GPIO)53power-down mode logic54triggering, wake-up, and effects54power-supply sequencing56system-level design considerations56power-supply design considerations57power-supply decoupling57IEEE 1149.1 JTAG compatibility statement58EMIF device speed59EMIF big endian mode correctness60bootmode61reset61absolute maximum ratings over operating case temperature range (unless otherwise noted)†62recommended operating conditions‡62electrical characteristics over recommended ranges of supply voltage and operating case temperature† ( unless otherwise noted)63PARAMETER MEASUREMENT INFORMATION64signal transition levels64AC transient rise/fall time specifications65timing parameters and board routing analysis66INPUT AND OUTPUT CLOCKS68timing requirements for CLKIN†‡§ (see Figure 22)68timing requirements for CLKIN†‡§ (see Figure 22)68switching characteristics over recommended operating conditions for CLKOUT2†‡ ( see Figure 23)69switching characteristics over recommended operating conditions for CLKOUT3†§ (see Figure 24)69timing requirements for ECLKIN† (see Figure 25)70switching characteristics over recommended operating conditions for ECLKOUT‡§¶ (see Figure 26)70ASYNCHRONOUS MEMORY TIMING71timing requirements for asynchronous memory cycles†‡§ (see Figure 27-Figure 28)71switching characteristics over recommended operating conditions for asynchronous memory cycles†‡§ (see Figure 27–Figure 28)71SYNCHRONOUS-BURST MEMORY TIMING74timing requirements for synchronous-burst SRAM cycles† (see Figure 29)74switching characteristics over recommended operating conditions for synchronous-burst SRAM cycles†‡ ( see Figure 29 and Figure 30)74SYNCHRONOUS DRAM TIMING76timing requirements for synchronous DRAM cycles† (see Figure 31)76switching characteristics over recommended operating conditions for synchronous DRAM cycles†‡ ( see Figure 31- Figure 37)76HOLD\/HOLDA\ TIMING82timing requirements for the HOLD\/HOLDA\ cycles† (see Figure 38)82switching characteristics over recommended operating conditions for the HOLD\/HOLDA\ cycles†‡ ( see Figure 38)82BUSREQ TIMING83switching characteristics over recommended operating conditions for the BUSREQ cycles ( see Figure 39)83RESET TIMING84timing requirements for reset†‡ (see Figure 40)84switching characteristics over recommended operating conditions during reset¶ (see Figure 40)84EXTERNAL INTERRUPT TIMING86timing requirements for external interrupts† (see Figure 41)86HOST-PORT INTERFACE TIMING87timing requirements for host-port interface cycles†‡ (see Figure 42, Figure 43, Figure 44, and Figure 45)87switching characteristics over recommended operating conditions during host-port interface cycles†‡ ( see Figure 42, Figure 43, Figure 44, and Figure 45)88MULTICHANNEL BUFFERED SERIAL PORT TIMING91timing requirements for McBSP†‡ (see Figure 46)91switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 46)92timing requirements for FSR when GSYNC = 1 (see Figure 47)94timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 48)94switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ ( see Figure 48)95timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 49)96switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ ( see Figure 49)96timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 50)97switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ ( see Figure 50)98timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 51)99switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ ( see Figure 51)99TIMER TIMING100timing requirements for timer inputs† (see Figure 52)100switching characteristics over recommended operating conditions for timer outputs† ( see Figure 52)100GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING101timing requirements for GPIO inputs†‡ (see Figure 53)101switching characteristics over recommended operating conditions for GPIO outputs†§ (see Figure 53)101JTAG TEST-PORT TIMING102timing requirements for JTAG test port (see Figure 54)102switching characteristics over recommended operating conditions for JTAG test port ( see Figure 54)102MECHANICAL DATA103package thermal resistance characteristics103thermal resistance characteristics (S-PBGA package) for GDP103thermal resistance characteristics (S-PBGA package) for ZDP103packaging information103文件大小: 1.4 MB页数: 107Language: English打开用户手册