用户手册目录NI 6124/6154 User Manual1Support2Worldwide Technical Support and Product Information2National Instruments Corporate Headquarters2Worldwide Offices2Important Information3Warranty3Copyright3Trademarks3Patents3WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS3Compliance4Contents5About This Manual11Conventions11Related Documentation12Chapter 1 Getting Started16Installing NI-DAQmx16Installing Other Software16Installing the Hardware17Device Self-Calibration17Device Pinouts18Device Specifications18Chapter 2 DAQ System Overview19Figure 2-1. Typical DAQ System19DAQ Hardware20Figure 2-2. General NI 6124 Block Diagram20Figure 2-3. General NI 6154 Block Diagram21DAQ-STC221Calibration Circuitry22Internal or Self-Calibration22External Calibration23Signal Conditioning23Sensors and Transducers23Programming Devices in Software24Chapter 3 I/O Connector25NI 6124 I/O Connector Signal Descriptions25Table 3-1. NI 6124 Device Signal Descriptions25NI 6154 I/O Connector Signal Descriptions26Table 3-2. NI 6154 I/O Connector Signal Descriptions26+5 V Power Source27Chapter 4 Analog Input28Figure 4-1. Non-Isolated S Series Analog Input Block Diagram28Figure 4-2. Isolated S Series Analog Input Block Diagram28Analog Input Terminal Configuration29Input Polarity and Range30Working Voltage Range31AI Data Acquisition Methods31Analog Input Triggering33Connecting Analog Input Signals33Table 4-1. S Series Analog Input Signal Configuration33Types of Signal Sources34Differential Connections for Ground-Referenced Signal Sources34Figure 4-3. Differential Connection for Ground-Referenced Signals on Non-Isolated Devices35Figure 4-4. Differential Connection for Ground-Referenced Signals on Isolated Devices35Common-Mode Signal Rejection Considerations36Differential Connections for Non-Referenced or Floating Signal Sources36Figure 4-5. Differential Connection for Non-Referenced Signals on Non-Isolated Devices36Figure 4-6. Differential Connection for Non-Referenced Signals on Isolated Devices37DC-Coupled37AC-Coupled38Field Wiring Considerations38Minimizing Drift in Differential Mode39Analog Input Timing Signals40Figure 4-7. Typical Posttriggered DAQ Sequence40Figure 4-8. Typical Pretriggered DAQ Sequence40AI Sample Clock Signal41Using an Internal Source41Using an External Source42Routing AI Sample Clock Signal to an Output Terminal42Other Timing Requirements42Figure 4-9. AI Sample Clock and AI Start Trigger43AI Sample Clock Timebase Signal43AI Convert Clock Signal43Using an Internal Source44Using an External Source44Routing AI Convert Clock Signal to an Output Terminal44AI Convert Clock Timebase Signal44AI Hold Complete Event Signal45AI Start Trigger Signal45Using a Digital Source45Using an Analog Source46Routing AI Start Trigger to an Output Terminal46AI Reference Trigger Signal46Figure 4-10. Reference Trigger Final Buffer47Using a Digital Source47Using an Analog Source47Routing AI Reference Trigger Signal to an Output Terminal47Getting Started with AI Applications in Software48Chapter 5 Analog Output49Figure 5-1. Non-Isolated S Series Device Analog Output Block Diagram49Figure 5-2. Isolated S Series Device Analog Output Block Diagram49Minimizing Glitches on the Output Signal50AO Data Generation Methods50Analog Output Triggering52Connecting Analog Output Signals52Figure 5-3. Analog Output Connections for Non-Isolated S Series Devices53Figure 5-4. Analog Output Connections for Isolated S Series Devices53Waveform Generation Timing Signals54Figure 5-5. Analog Output Engine Routing Options54AO Sample Clock Signal54Using an Internal Source54Using an External Source55Figure 5-6. AO Sample Clock Timing Requirements55Routing AO Sample Clock Signal to an Output Terminal55Other Timing Requirements55Figure 5-7. AO Sample Clock and AO Start Trigger56AO Sample Clock Timebase Signal56Figure 5-8. AO Sample Clock Timebase Timing Requirements57AO Start Trigger Signal57Using a Digital Source57Figure 5-9. AO Start Trigger Timing Requirements58Using an Analog Source58Routing AO Start Trigger Signal to an Output Terminal58AO Pause Trigger Signal58Using a Digital Source59Using an Analog Source59Getting Started with AO Applications in Software59Chapter 6 Digital I/O60Digital I/O for Non-Isolated Devices60Figure 6-1. Non-Isolated S Series Digital I/O Circuitry61Static DIO for Non-Isolated Devices61Digital Waveform Triggering for Non-Isolated Devices62Figure 6-2. Digital Waveform Triggering62Digital Waveform Acquisition for Non-Isolated Devices62DI Sample Clock Signal63Digital Waveform Generation for Non-Isolated Devices64DO Sample Clock Signal64I/O Protection for Non-Isolated Devices66Programmable Power-Up States for Non-Isolated Devices66DI Change Detection for Non-Isolated Devices67Figure 6-3. DI Change Detection67DI Change Detection Applications for Non-Isolated Devices68Connecting Digital I/O Signals on Non-Isolated Devices68Figure 6-4. Digital I/O Connections69Getting Started with DIO Applications in Software on Non-Isolated Devices69Digital I/O for Isolated Devices70Figure 6-5. Isolated S Series Devices Digital I/O Block Diagram70Static DIO for Isolated Devices70I/O Protection for Isolated Devices71Connecting Digital I/O Signals on Isolated Devices71Figure 6-6. Isolated S Series Device Digital I/O Signal Connections72Getting Started with DIO Applications in Software on Isolated Devices72Chapter 7 Counters73Figure 7-1. S Series Counters73Counter Input Applications74Counting Edges74Single Point (On-Demand) Edge Counting74Figure 7-2. Single Point (On-Demand) Edge Counting74Figure 7-3. Single Point (On-Demand) Edge Counting with Pause Trigger75Buffered (Sample Clock) Edge Counting75Figure 7-4. Buffered (Sample Clock) Edge Counting75Controlling the Direction of Counting76Pulse-Width Measurement76Single Pulse-Width Measurement76Figure 7-5. Single Pulse-Width Measurement77Buffered Pulse-Width Measurement77Figure 7-6. Buffered Pulse-Width Measurement77Period Measurement78Single Period Measurement78Figure 7-7. Single Period Measurement78Buffered Period Measurement79Figure 7-8. Buffered Period Measurement79Semi-Period Measurement79Single Semi-Period Measurement80Buffered Semi-Period Measurement80Figure 7-9. Buffered Semi-Period Measurement80Frequency Measurement81Figure 7-10. Method 181Figure 7-11. Method 1b82Figure 7-12. Method 283Figure 7-13. Method 384Choosing a Method for Measuring Frequency84Table 7-1. Frequency Measurement Method 185Table 7-2. Frequency Measurement Method Comparison86Position Measurement86Measurements Using Quadrature Encoders86Figure 7-14. X1 Encoding87Figure 7-15. X2 Encoding87Figure 7-16. X4 Encoding87Figure 7-17. Channel Z Reload with X4 Decoding88Measurements Using Two Pulse Encoders88Figure 7-18. Measurements Using Two Pulse Encoders88Buffered (Sample Clock) Position Measurement89Figure 7-19. Buffered Position Measurement89Two-Signal Edge-Separation Measurement89Single Two-Signal Edge-Separation Measurement90Figure 7-20. Single Two-Signal Edge-Separation Measurement90Buffered Two-Signal Edge-Separation Measurement90Figure 7-21. Buffered Two-Signal Edge-Separation Measurement91Counter Output Applications91Simple Pulse Generation91Single Pulse Generation91Figure 7-22. Single Pulse Generation92Single Pulse Generation with Start Trigger92Figure 7-23. Single Pulse Generation with Start Trigger92Retriggerable Single Pulse Generation92Figure 7-24. Retriggerable Single Pulse Generation93Pulse Train Generation93Continuous Pulse Train Generation93Figure 7-25. Continuous Pulse Train Generation94Finite Pulse Train Generation94Figure 7-26. Finite Pulse Train Timing Diagram94Frequency Generation95Using the Frequency Generator95Figure 7-27. Frequency Generator Block Diagram95Figure 7-28. Frequency Generator Output Waveform95Frequency Division96Pulse Generation for ETS96Figure 7-29. Pulse Generation for ETS97Counter Timing Signals97Counter n Source Signal98Table 7-3. Counter Applications and Counter n Source98Routing a Signal to Counter n Source98Routing Counter n Source to an Output Terminal99Counter n Gate Signal99Routing a Signal to Counter n Gate99Routing Counter n Gate to an Output Terminal99Counter n Aux Signal100Routing a Signal to Counter n Aux100Counter n A, Counter n B, and Counter n Z Signals100Routing Signals to A, B, and Z Counter Inputs100Routing Counter n Z Signal to an Output Terminal100Counter n Up_Down Signal101Counter n HW Arm Signal101Routing Signals to Counter n HW Arm Input101Counter n Internal Output and Counter n TC Signals101Routing Counter n Internal Output to an Output Terminal102Frequency Output Signal102Routing Frequency Output to a Terminal102Default Counter/Timer Pinouts102Counter Triggering103Other Counter Features104Cascading Counters104Counter Filters104Table 7-4. Filters104Figure 7-30. Filter Example105Prescaling105Figure 7-31. Prescaling106Duplicate Count Prevention106Example Application That Works Correctly (No Duplicate Counting)107Figure 7-32. Duplicate Count Prevention Example107Example Application That Works Incorrectly (Duplicate Counting)108Figure 7-33. Duplicate Count Example108Example Application That Prevents Duplicate Count108Figure 7-34. Duplicate Count Prevention Example108When To Use Duplicate Count Prevention109Enabling Duplicate Count Prevention in NI-DAQmx109Synchronization Modes109Table 7-5. Synchronization Mode Conditions11080 MHz Source Mode110Figure 7-35. 80 MHz Source Mode110Other Internal Source Mode111Figure 7-36. Other Internal Source Mode111External Source Mode111Figure 7-37. External Source Mode111Chapter 8 Programmable Function Interfaces (PFI)112PFI for Non-Isolated Devices112Figure 8-1. PFI Circuitry on Non-Isolated S Series Devices113PFI for Isolated Devices113Figure 8-2. PFI Input Circuitry on Isolated S Series Devices114Figure 8-3. PFI Output Circuitry on Isolated S Series Devices114Using PFI Terminals as Timing Input Signals115Exporting Timing Output Signals Using PFI Terminals115Using PFI Terminals as Static Digital Inputs and Outputs116Connecting PFI Input Signals117Figure 8-4. PFI Input Signals Connections117PFI Filters117Table 8-1. Filters118Figure 8-5. Filter Example118I/O Protection119Programmable Power-Up States119Chapter 9 Digital Routing and Clock Generation121Clock Routing121Figure 9-1. S Series Clock Routing Circuitry12180 MHz Timebase12220 MHz Timebase122100 kHz Timebase122External Reference Clock12210 MHz Reference Clock123Synchronizing Multiple Devices123Real-Time System Integration (RTSI)124RTSI Connector Pinout124Table 9-1. RTSI Signals124Figure 9-2. S Series PCI Device RTSI Pinout125Using RTSI as Outputs125Using RTSI Terminals as Timing Input Signals126RTSI Filters126Table 9-2. Filters127Figure 9-3. Filter Example127PXI Clock and Trigger Signals128PXI_CLK10128PXI Triggers128PXI_STAR Trigger128PXI_STAR Filters129Table 9-3. Filters129Figure 9-4. Filter Example130Routing Signals in Software130Table 9-4. Signal Routing in Software130Chapter 10 Bus Interface131MITE and DAQ-PnP131PXI Considerations131PXI Clock and Trigger Signals131PXI Express131Data Transfer Methods132Changing Data Transfer Methods between DMA and IRQ132Chapter 11 Triggering133Triggering with a Digital Source133Figure 11-1. Falling-Edge Trigger134Triggering with an Analog Source134Figure 11-2. Analog Trigger Circuitry134Analog Input Channel135Analog Trigger Actions135Analog Trigger Types135Figure 11-3. Below-Level Analog Triggering Mode136Figure 11-4. Above-Level Analog Triggering Mode136Figure 11-5. Analog Edge Triggering with Hysteresis Rising Slope Example137Figure 11-6. Analog Edge Triggering with Hysteresis Falling Slope Example137Figure 11-7. Analog Window Triggering Mode (Entering Window)138Analog Trigger Accuracy138Appendix A Device-Specific Information139Figure A-1. NI 6124 Pinout140Table A-1. Default NI-DAQmx Counter/Timer Pins141Figure A-2. NI 6124 Block Diagram142Figure A-3. NI 6154 Pinout146Table A-2. NI 6154 Device Default NI-DAQmx Counter/Timer Pins146Figure A-4. NI 6154 Block Diagram148Table A-3. Ground Symbols149Appendix B Technical Support and Professional Services152Glossary154Symbols154A154B-C155D157E-F158G-L159M-P160Q-R161S-T162V163Index165Numerics165A165B-C166D167E-F168G-M169N-P170Q-S171T172U-X173文件大小: 2.6 MB页数: 173Language: English打开用户手册
用户手册目录NI 6124/6154 User Manual1Support2Worldwide Technical Support and Product Information2National Instruments Corporate Headquarters2Worldwide Offices2Important Information3Warranty3Copyright3Trademarks3Patents3WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS3Compliance4Contents5About This Manual11Conventions11Related Documentation12Chapter 1 Getting Started16Installing NI-DAQmx16Installing Other Software16Installing the Hardware17Device Self-Calibration17Device Pinouts18Device Specifications18Chapter 2 DAQ System Overview19Figure 2-1. Typical DAQ System19DAQ Hardware20Figure 2-2. General NI 6124 Block Diagram20Figure 2-3. General NI 6154 Block Diagram21DAQ-STC221Calibration Circuitry22Internal or Self-Calibration22External Calibration23Signal Conditioning23Sensors and Transducers23Programming Devices in Software24Chapter 3 I/O Connector25NI 6124 I/O Connector Signal Descriptions25Table 3-1. NI 6124 Device Signal Descriptions25NI 6154 I/O Connector Signal Descriptions26Table 3-2. NI 6154 I/O Connector Signal Descriptions26+5 V Power Source27Chapter 4 Analog Input28Figure 4-1. Non-Isolated S Series Analog Input Block Diagram28Figure 4-2. Isolated S Series Analog Input Block Diagram28Analog Input Terminal Configuration29Input Polarity and Range30Working Voltage Range31AI Data Acquisition Methods31Analog Input Triggering33Connecting Analog Input Signals33Table 4-1. S Series Analog Input Signal Configuration33Types of Signal Sources34Differential Connections for Ground-Referenced Signal Sources34Figure 4-3. Differential Connection for Ground-Referenced Signals on Non-Isolated Devices35Figure 4-4. Differential Connection for Ground-Referenced Signals on Isolated Devices35Common-Mode Signal Rejection Considerations36Differential Connections for Non-Referenced or Floating Signal Sources36Figure 4-5. Differential Connection for Non-Referenced Signals on Non-Isolated Devices36Figure 4-6. Differential Connection for Non-Referenced Signals on Isolated Devices37DC-Coupled37AC-Coupled38Field Wiring Considerations38Minimizing Drift in Differential Mode39Analog Input Timing Signals40Figure 4-7. Typical Posttriggered DAQ Sequence40Figure 4-8. Typical Pretriggered DAQ Sequence40AI Sample Clock Signal41Using an Internal Source41Using an External Source42Routing AI Sample Clock Signal to an Output Terminal42Other Timing Requirements42Figure 4-9. AI Sample Clock and AI Start Trigger43AI Sample Clock Timebase Signal43AI Convert Clock Signal43Using an Internal Source44Using an External Source44Routing AI Convert Clock Signal to an Output Terminal44AI Convert Clock Timebase Signal44AI Hold Complete Event Signal45AI Start Trigger Signal45Using a Digital Source45Using an Analog Source46Routing AI Start Trigger to an Output Terminal46AI Reference Trigger Signal46Figure 4-10. Reference Trigger Final Buffer47Using a Digital Source47Using an Analog Source47Routing AI Reference Trigger Signal to an Output Terminal47Getting Started with AI Applications in Software48Chapter 5 Analog Output49Figure 5-1. Non-Isolated S Series Device Analog Output Block Diagram49Figure 5-2. Isolated S Series Device Analog Output Block Diagram49Minimizing Glitches on the Output Signal50AO Data Generation Methods50Analog Output Triggering52Connecting Analog Output Signals52Figure 5-3. Analog Output Connections for Non-Isolated S Series Devices53Figure 5-4. Analog Output Connections for Isolated S Series Devices53Waveform Generation Timing Signals54Figure 5-5. Analog Output Engine Routing Options54AO Sample Clock Signal54Using an Internal Source54Using an External Source55Figure 5-6. AO Sample Clock Timing Requirements55Routing AO Sample Clock Signal to an Output Terminal55Other Timing Requirements55Figure 5-7. AO Sample Clock and AO Start Trigger56AO Sample Clock Timebase Signal56Figure 5-8. AO Sample Clock Timebase Timing Requirements57AO Start Trigger Signal57Using a Digital Source57Figure 5-9. AO Start Trigger Timing Requirements58Using an Analog Source58Routing AO Start Trigger Signal to an Output Terminal58AO Pause Trigger Signal58Using a Digital Source59Using an Analog Source59Getting Started with AO Applications in Software59Chapter 6 Digital I/O60Digital I/O for Non-Isolated Devices60Figure 6-1. Non-Isolated S Series Digital I/O Circuitry61Static DIO for Non-Isolated Devices61Digital Waveform Triggering for Non-Isolated Devices62Figure 6-2. Digital Waveform Triggering62Digital Waveform Acquisition for Non-Isolated Devices62DI Sample Clock Signal63Digital Waveform Generation for Non-Isolated Devices64DO Sample Clock Signal64I/O Protection for Non-Isolated Devices66Programmable Power-Up States for Non-Isolated Devices66DI Change Detection for Non-Isolated Devices67Figure 6-3. DI Change Detection67DI Change Detection Applications for Non-Isolated Devices68Connecting Digital I/O Signals on Non-Isolated Devices68Figure 6-4. Digital I/O Connections69Getting Started with DIO Applications in Software on Non-Isolated Devices69Digital I/O for Isolated Devices70Figure 6-5. Isolated S Series Devices Digital I/O Block Diagram70Static DIO for Isolated Devices70I/O Protection for Isolated Devices71Connecting Digital I/O Signals on Isolated Devices71Figure 6-6. Isolated S Series Device Digital I/O Signal Connections72Getting Started with DIO Applications in Software on Isolated Devices72Chapter 7 Counters73Figure 7-1. S Series Counters73Counter Input Applications74Counting Edges74Single Point (On-Demand) Edge Counting74Figure 7-2. Single Point (On-Demand) Edge Counting74Figure 7-3. Single Point (On-Demand) Edge Counting with Pause Trigger75Buffered (Sample Clock) Edge Counting75Figure 7-4. Buffered (Sample Clock) Edge Counting75Controlling the Direction of Counting76Pulse-Width Measurement76Single Pulse-Width Measurement76Figure 7-5. Single Pulse-Width Measurement77Buffered Pulse-Width Measurement77Figure 7-6. Buffered Pulse-Width Measurement77Period Measurement78Single Period Measurement78Figure 7-7. Single Period Measurement78Buffered Period Measurement79Figure 7-8. Buffered Period Measurement79Semi-Period Measurement79Single Semi-Period Measurement80Buffered Semi-Period Measurement80Figure 7-9. Buffered Semi-Period Measurement80Frequency Measurement81Figure 7-10. Method 181Figure 7-11. Method 1b82Figure 7-12. Method 283Figure 7-13. Method 384Choosing a Method for Measuring Frequency84Table 7-1. Frequency Measurement Method 185Table 7-2. Frequency Measurement Method Comparison86Position Measurement86Measurements Using Quadrature Encoders86Figure 7-14. X1 Encoding87Figure 7-15. X2 Encoding87Figure 7-16. X4 Encoding87Figure 7-17. Channel Z Reload with X4 Decoding88Measurements Using Two Pulse Encoders88Figure 7-18. Measurements Using Two Pulse Encoders88Buffered (Sample Clock) Position Measurement89Figure 7-19. Buffered Position Measurement89Two-Signal Edge-Separation Measurement89Single Two-Signal Edge-Separation Measurement90Figure 7-20. Single Two-Signal Edge-Separation Measurement90Buffered Two-Signal Edge-Separation Measurement90Figure 7-21. Buffered Two-Signal Edge-Separation Measurement91Counter Output Applications91Simple Pulse Generation91Single Pulse Generation91Figure 7-22. Single Pulse Generation92Single Pulse Generation with Start Trigger92Figure 7-23. Single Pulse Generation with Start Trigger92Retriggerable Single Pulse Generation92Figure 7-24. Retriggerable Single Pulse Generation93Pulse Train Generation93Continuous Pulse Train Generation93Figure 7-25. Continuous Pulse Train Generation94Finite Pulse Train Generation94Figure 7-26. Finite Pulse Train Timing Diagram94Frequency Generation95Using the Frequency Generator95Figure 7-27. Frequency Generator Block Diagram95Figure 7-28. Frequency Generator Output Waveform95Frequency Division96Pulse Generation for ETS96Figure 7-29. Pulse Generation for ETS97Counter Timing Signals97Counter n Source Signal98Table 7-3. Counter Applications and Counter n Source98Routing a Signal to Counter n Source98Routing Counter n Source to an Output Terminal99Counter n Gate Signal99Routing a Signal to Counter n Gate99Routing Counter n Gate to an Output Terminal99Counter n Aux Signal100Routing a Signal to Counter n Aux100Counter n A, Counter n B, and Counter n Z Signals100Routing Signals to A, B, and Z Counter Inputs100Routing Counter n Z Signal to an Output Terminal100Counter n Up_Down Signal101Counter n HW Arm Signal101Routing Signals to Counter n HW Arm Input101Counter n Internal Output and Counter n TC Signals101Routing Counter n Internal Output to an Output Terminal102Frequency Output Signal102Routing Frequency Output to a Terminal102Default Counter/Timer Pinouts102Counter Triggering103Other Counter Features104Cascading Counters104Counter Filters104Table 7-4. Filters104Figure 7-30. Filter Example105Prescaling105Figure 7-31. Prescaling106Duplicate Count Prevention106Example Application That Works Correctly (No Duplicate Counting)107Figure 7-32. Duplicate Count Prevention Example107Example Application That Works Incorrectly (Duplicate Counting)108Figure 7-33. Duplicate Count Example108Example Application That Prevents Duplicate Count108Figure 7-34. Duplicate Count Prevention Example108When To Use Duplicate Count Prevention109Enabling Duplicate Count Prevention in NI-DAQmx109Synchronization Modes109Table 7-5. Synchronization Mode Conditions11080 MHz Source Mode110Figure 7-35. 80 MHz Source Mode110Other Internal Source Mode111Figure 7-36. Other Internal Source Mode111External Source Mode111Figure 7-37. External Source Mode111Chapter 8 Programmable Function Interfaces (PFI)112PFI for Non-Isolated Devices112Figure 8-1. PFI Circuitry on Non-Isolated S Series Devices113PFI for Isolated Devices113Figure 8-2. PFI Input Circuitry on Isolated S Series Devices114Figure 8-3. PFI Output Circuitry on Isolated S Series Devices114Using PFI Terminals as Timing Input Signals115Exporting Timing Output Signals Using PFI Terminals115Using PFI Terminals as Static Digital Inputs and Outputs116Connecting PFI Input Signals117Figure 8-4. PFI Input Signals Connections117PFI Filters117Table 8-1. Filters118Figure 8-5. Filter Example118I/O Protection119Programmable Power-Up States119Chapter 9 Digital Routing and Clock Generation121Clock Routing121Figure 9-1. S Series Clock Routing Circuitry12180 MHz Timebase12220 MHz Timebase122100 kHz Timebase122External Reference Clock12210 MHz Reference Clock123Synchronizing Multiple Devices123Real-Time System Integration (RTSI)124RTSI Connector Pinout124Table 9-1. RTSI Signals124Figure 9-2. S Series PCI Device RTSI Pinout125Using RTSI as Outputs125Using RTSI Terminals as Timing Input Signals126RTSI Filters126Table 9-2. Filters127Figure 9-3. Filter Example127PXI Clock and Trigger Signals128PXI_CLK10128PXI Triggers128PXI_STAR Trigger128PXI_STAR Filters129Table 9-3. Filters129Figure 9-4. Filter Example130Routing Signals in Software130Table 9-4. Signal Routing in Software130Chapter 10 Bus Interface131MITE and DAQ-PnP131PXI Considerations131PXI Clock and Trigger Signals131PXI Express131Data Transfer Methods132Changing Data Transfer Methods between DMA and IRQ132Chapter 11 Triggering133Triggering with a Digital Source133Figure 11-1. Falling-Edge Trigger134Triggering with an Analog Source134Figure 11-2. Analog Trigger Circuitry134Analog Input Channel135Analog Trigger Actions135Analog Trigger Types135Figure 11-3. Below-Level Analog Triggering Mode136Figure 11-4. Above-Level Analog Triggering Mode136Figure 11-5. Analog Edge Triggering with Hysteresis Rising Slope Example137Figure 11-6. Analog Edge Triggering with Hysteresis Falling Slope Example137Figure 11-7. Analog Window Triggering Mode (Entering Window)138Analog Trigger Accuracy138Appendix A Device-Specific Information139Figure A-1. NI 6124 Pinout140Table A-1. Default NI-DAQmx Counter/Timer Pins141Figure A-2. NI 6124 Block Diagram142Figure A-3. NI 6154 Pinout146Table A-2. NI 6154 Device Default NI-DAQmx Counter/Timer Pins146Figure A-4. NI 6154 Block Diagram148Table A-3. Ground Symbols149Appendix B Technical Support and Professional Services152Glossary154Symbols154A154B-C155D157E-F158G-L159M-P160Q-R161S-T162V163Index165Numerics165A165B-C166D167E-F168G-M169N-P170Q-S171T172U-X173文件大小: 2.6 MB页数: 173Language: English打开用户手册