用户手册目录Lab-PC+1Limited Warranty3Copyright3Trademarks3Medical Warning4Contents5About This Manual10Organization of the Lab-PC+ User Manual10Conventions Used in This Manual11National Instruments Documentation12Customer Communication12Chapter 1 Introduction13About the Lab-PC+13What You Need to Get Started13Software Programming Choices14LabVIEW and LabWindows/CVI Application Software14NI-DAQ Driver Software14Register-Level Programming15Optional Equipment16Unpacking16Chapter 2 Configuration and Installation17Board Configuration17PC Bus Interface17Base I/O Address Selection19DMA Channel Selection22Interrupt Selection23Analog I/O Configuration24Analog Output Configuration25Bipolar Output Selection25Unipolar Output Selection26Analog Input Configuration26Input Mode26DIFF Input (Four Channels27RSE Input (Eight Channels, Factory Setting)28NRSE Input (Eight Channels)29Analog Input Polarity Configuration29Bipolar Input Selection29Unipolar Input Selection30Hardware Installation31Chapter 3 Signal Connections32I/O Connector Pin Description32Signal Connection Descriptions33Analog Input Signal Connections35Types of Signal Sources36Floating Signal Sources36Ground-Referenced Signal Sources37Input Configurations37Differential Connection Considerations (DIFF Configuration)37Differential Connections for Grounded Signal Sources38Differential Connections for Floating Signal Sources39Single-Ended Connection Considerations41Single-Ended Connections for Floating Signal Sources (RSE Configuration)41Single-Ended Connections for Grounded Signal Sources (NRSE Configuration)42Common-Mode Signal Rejection Considerations43Analog Output Signal Connections43Digital I/O Signal Connections44Port C Pin Connections46Timing Specifications47Mode 1 Input Timing49Mode 1 Output Timing50Mode 2 Bidirectional Timing51Timing Connections52Data Acquisition Timing Connections52General-Purpose Timing Signal Connections and General-Purpose Counter/Timing Signals55Cabling59Chapter 4 Theory of Operation60Functional Overview60PC I/O Channel Interface Circuitry61Analog Input and Data Acquisition Circuitry63Analog Input Circuitry64Data Acquisition Timing Circuitry64Single-Channel Data Acquisition65Multiple-Channel (Scanned) Data Acquisition65Data Acquisition Rates66Analog Output Circuitry68Digital I/O Circuitry69Timing I/O Circuitry70Chapter 5 Calibration74Calibration Equipment Requirements74Calibration Trimpots75Analog Input Calibration76Board Configuration77Bipolar Input Calibration Procedure77Unipolar Input Calibration Procedure78Analog Output Calibration79Board Configuration79Bipolar Output Calibration Procedure79Unipolar Output Calibration Procedure81Adjust the Analog Output Gain81Appendix A Specifications82Analog Input82Input Characteristics82Transfer Characteristics82Amplifier Characteristics83Dynamic Characteristics83Stability83Explanation of Analog Input Specifications84Analog Output85Output Characteristics85Transfer Characteristics85Voltage Output85Dynamic Characteristics85Stability85Explanation of Analog Output Specifications85Digital I/O86Timing I/O86Triggers87Digital Trigger87Bus Interface87Power Requirements (from PC)87Physical87Environment87Appendix B OKI 82C53 Data Sheet88Appendix C OKI 82C55A Data Sheet100Appendix D Register Map and Descriptions117Register Map117Register Sizes119Register Description119Register Description Format119Configuration and Status Register Group120Command Register 1121Status Register123Command Register 2125Command Register 3127Command Register 4129Analog Input Register Group131A/D FIFO Register132A/D Clear Register134Start Convert Register135DMATC Interrupt Clear Register136Analog Output Register Group137DAC0 Low-Byte (DAC0L), DAC0 High-Byte (DAC0H), DAC1 Low-Byte (DAC1L), and DAC1 High-Byte (DAC1H) Registers1388253 Counter/Timer Register Groups A and B139Counter A0 Data Register140Counter A1 Data Register141Counter A2 Data Register142Counter A Mode Register143Timer Interrupt Clear Register144Counter B0 Data Register145Counter B1 Data Register146Counter B2 Data Register147Counter B Mode Register1488255A Digital I/O Register Group149Port A Register150Port B Register151Port C Register152Digital Control Register153Interval Counter Register Group154Interval Counter Data Register155Interval Counter Strobe Register156Appendix E Register-Level Programming157Register Programming Considerations157Initializing the Lab-PC+ Board157Programming the Analog Input Circuitry158Analog Input Circuitry Programming Sequence159A/D FIFO Output Binary Modes160Clearing the Analog Input Circuitry161Programming Multiple A/D Conversions on a Single Input Channel161Programming in Controlled Acquisition Mode162Programming in Freerun Acquisition Mode164External Timing Considerations for Multiple A/D Conversions167Using the EXTTRIG Signal to Initiate a Multiple A/D Conversion Data Acquisition Operation (Posttrigger Mode)167Using the EXTTRIG Signal to Terminate a Multiple A/D Conversion Data Acquisition Operation (Pretrigger Mode)167Using the EXTCONV* Signal to Initiate A/D Conversions168Programming Multiple A/D Conversions Using External Timing168Programming in Controlled Acquisition Mode168Posttrigger Mode168Pretrigger Mode170Programming in Freerun Acquisition Mode172Posttrigger Mode172Pretrigger Mode173Programming Multiple A/D Conversions with Channel Scanning173Programming Multiple A/D Conversions with Interval Scanning173Programming Multiple A/D Conversions in Single-Channel Interval Acquisition Mode174A/D Interrupt Programming175Programming DMA Operation176Programming the Analog Output Circuitry176Interrupt Programming for the Analog Output Circuitry178Programming the Digital I/O Circuitry179Register Descriptions and Programming Examples179Modes of Operation for the 8255A181Mode 0181Control Words181Programming Examples182Mode 1183Input183Programming Example185Output185Programming Example187Mode 2187Control Words187Programming Example189Single Bit Set/Reset Control Words189Single Bit Set/Reset Feature190Interrupt Programming for the Digital I/O Circuitry190Appendix F Customer Communication191Index197Glossary195Figures8Figure 1-1. The Relationship between the Programming Environment, NI-DAQ, and Your Hardware15Figure 2-1. Parts Locator Diagram18Figure 2-2. Example Base I/O Address Switch Settings20Figure 2-3. DMA Jumper Settings for DMA Channel 3 (Factory Setting)22Figure 2-4. DMA Jumper Settings for Disabling DMA Transfers23Figure 2-5. Interrupt Jumper Setting IRQ5 (Factory Setting)23Figure 2-6. Interrupt Jumper Setting for Disabling Interrupts24Figure 2-7. Bipolar Output Jumper Configuration (Factory Setting)25Figure 2-8. Unipolar Output Jumper Configuration26Figure 2-9. DIFF Input Configuration28Figure 2-10. RSE Input Configuration28Figure 2-11. NRSE Input Configuration29Figure 2-12. Bipolar Input Jumper Configuration (Factory Setting)30Figure 2-13. Unipolar Input Jumper Configuration30Figure 3-1. Lab-PC+ I/O Connector Pin Assignments33Figure 3-2. Lab-PC+ Instrumentation Amplifier36Figure 3-3. Differential Input Connections for Grounded Signal Sources39Figure 3-4. Differential Input Connections for Floating Sources40Figure 3-5. Single-Ended Input Connections for Floating Signal Sources42Figure 3-6. Single-Ended Input Connections for Grounded Signal Sources43Figure 3-7. Analog Output Signal Connections44Figure 3-8. Digital I/O Connections46Figure 3-9. EXTCONV* Signal Timing52Figure 3-10. Posttrigger Data Acquisition Timing Case 153Figure 3-11. Posttrigger Data Acquisition Timing Case 253Figure 3-12. Pretrigger Data Acquisition Timing54Figure 3-13. EXTUPDATE* Signal Timing for Updating DAC Output55Figure 3-14. EXTUPDATE* Signal Timing for Generating Interrupts55Figure 3-15. Event-Counting Application with External Switch Gating56Figure 3-16. Frequency Measurement Application57Figure 3-17. General-Purpose Timing Signals58Figure 4-1. Lab-PC+ Block Diagram60Figure 4-2. PC I/O Interface Circuitry Block Diagram62Figure 4-3. Analog Input and Data Acquisition Circuitry Block Diagram63Figure 4-4. Analog Output Circuitry Block Diagram68Figure 4-5. Digital I/O Circuitry Block Diagram69Figure 4-6. Timing I/O Circuitry Block Diagram71Figure 4-7. Two-Channel Interval-Scanning Timing72Figure 4-8. Single-Channel Interval Timing73Figure 4-9. Counter Block Diagram73Figure 5-1. Calibration Trimpot Location Diagram75Figure E-1. Control-Word Format with Control-Word Flag Set to 1180Figure E-2. Control-Word Format with Control-Word Flag Set to 0180Tables9Table 2-1. PC Bus Interface Factory Settings19Table 2-2. Switch Settings with Corresponding Base I/O Address and Base I/O Address Space21Table 2-3. DMA Channels for the Lab-PC+22Table 2-4. Analog I/O Jumper Settings25Table 2-5. Input Configurations Available for the Lab-PC+27Table 3-1. Recommended Input Configurations for Ground-Referenced and Floating Signal Sources37Table 3-2. Port C Signal Assignments47Table 4-1. Analog Input Settling Time Versus Gain66Table 4-2. Lab-PC+ Maximum Recommended Data Acquisition Rates67Table 4-3. Bipolar Analog Input Signal Range Versus Gain67Table 4-4. Unipolar Analog Input Signal Range Versus Gain67Table 5-1. Voltage Values of ADC Input77Table D-1. Lab-PC+ Register Map118Table E-1. Unipolar Input Mode A/D Conversion Values (Straight Binary Coding)160Table E-2. Bipolar Input Mode A/D Conversion Values (Two’s Complement Coding)160Table E-3. Analog Output Voltage Versus Digital Code (Unipolar Mode, Straight Binary Coding)177Table E-4. Analog Output Voltage Versus Digital Code (Bipolar Mode, Two’s Complement Coding)178Table E-5. ModeÊ0 I/O Configurations182Table E-6. Port C Set/Reset Control Words189文件大小: 2.9 MB页数: 211Language: English打开用户手册