用户手册目录NI 6232/6233 User Manual1Support2Worldwide Technical Support and Product Information2National Instruments Corporate Headquarters2Worldwide Offices2Important Information3Warranty3Copyright3Trademarks3Patents3WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS3Compliance5Contents6About This Manual13Conventions13Related Documentation14NI-DAQ14NI-DAQmx for Linux14NI-DAQmx Base15LabVIEW15LabWindows™/CVI™16Measurement Studio16ANSI C without NI Application Software16.NET Languages without NI Application Software16Device Documentation and Specifications17Training Courses17Technical Support on the Web17Chapter 1 Getting Started18Installing NI-DAQmx18Installing Other Software18Installing the Hardware18Device Pinouts18Device Specifications19Device Accessories and Cables19Chapter 2 DAQ System Overview20Figure 2-1. Components of a Typical DAQ System20DAQ Hardware20Figure 2-2. General NI 6232/6233 Block Diagram21DAQ-STC221Calibration Circuitry22Sensors and Transducers22Cables and Accessories23Custom Cabling23Programming Devices in Software24Chapter 3 Connector Information25I/O Connector Signal Descriptions25Table 3-1. I/O Connector Signals25RTSI Connector Pinout27Chapter 4 Analog Input28Figure 4-1. NI 6232/6233 Analog Input Circuitry28Analog Input Circuitry28Analog Input Range29Table 4-1. Input Ranges for NI 6232/623330Analog Input Ground-Reference Settings30Table 4-2. Analog Input Ground-Reference Settings31Figure 4-2. PGIA31Table 4-3. Signals Routed to the NI-PGIA32Configuring AI Ground-Reference Settings in Software32Figure 4-3. Enabling Multimode Scanning in LabVIEW33Multichannel Scanning Considerations33Use Low Impedance Sources33Use Short High-Quality Cabling34Carefully Choose the Channel Scanning Order34Avoid Switching from a Large to a Small Input Range34Insert Grounded Channel between Signal Channels35Minimize Voltage Step between Adjacent Channels35Avoid Scanning Faster Than Necessary36Example 136Example 236Analog Input Data Acquisition Methods36Software-Timed Acquisitions36Hardware-Timed Acquisitions37Buffered37Non-Buffered38Analog Input Triggering38Connecting Analog Voltage Input Signals38Table 4-4. Analog Input Configuration39Types of Signal Sources39Floating Signal Sources40Ground-Referenced Signal Sources40Differential Connection Considerations40Differential Connections for Ground-Referenced Signal Sources41Figure 4-4. Differential Connections for Ground-Referenced Signal Sources41Differential Input Biasing42Differential Connections for Non-Referenced or Floating Signal Sources42Figure 4-5. Differential Connections for Floating Signal Sources43Single-Ended Connection Considerations43Single-Ended Connections for Floating or Grounded Signal Sources44Figure 4-6. Single-Ended Connections for Floating Signal Sources (RSE Configuration)45Field Wiring Considerations45Analog Input Timing Signals46Figure 4-7. Analog Input Timing Options46Figure 4-8. Interval Sampling47Figure 4-9. Posttriggered Data Acquisition Example48Figure 4-10. Pretriggered Data Acquisition Example49AI Sample Clock Signal49Using an Internal Source50Using an External Source50Routing AI Sample Clock Signal to an Output Terminal50Other Timing Requirements50Figure 4-11. ai/SampleClock and ai/StartTrigger51AI Sample Clock Timebase Signal51AI Convert Clock Signal52Using an Internal Source52Using an External Source53Routing AI Convert Clock Signal to an Output Terminal53Using a Delay from Sample Clock to Convert Clock53Figure 4-12. ai/SampleClock and ai/ConvertClock53Other Timing Requirements54Figure 4-13. Single External Signal Driving ai/SampleClock and ai/ConvertClock Simultaneously54AI Convert Clock Timebase Signal54AI Hold Complete Event Signal55AI Start Trigger Signal55Using a Digital Source55Routing AI Start Trigger to an Output Terminal56AI Reference Trigger Signal56Figure 4-14. Reference Trigger Final Buffer57Using a Digital Source57Routing AI Reference Trigger Signal to an Output Terminal57AI Pause Trigger Signal57Using a Digital Source58Routing AI Pause Trigger Signal to an Output Terminal58Getting Started with AI Applications in Software58Chapter 5 Analog Output59Figure 5-1. NI 6232/6233 Analog Output Circuitry59Analog Output Circuitry59Minimizing Glitches on the Output Signal60Analog Output Data Generation Methods60Software-Timed Generations60Hardware-Timed Generations61Non-Buffered61Buffered61Analog Output Triggering62Connecting Analog Voltage Output Signals62Figure 5-2. Analog Output Connections63Analog Output Timing Signals63Figure 5-3. Analog Output Timing Options64AO Start Trigger Signal64Using a Digital Source64Routing AO Start Trigger Signal to an Output Terminal65AO Pause Trigger Signal65Figure 5-4. ao/PauseTrigger with the Onboard Clock Source65Figure 5-5. ao/PauseTrigger with Other Signal Source66Using a Digital Source66Routing AO Pause Trigger Signal to an Output Terminal66AO Sample Clock Signal66Using an Internal Source67Using an External Source67Routing AO Sample Clock Signal to an Output Terminal67Other Timing Requirements67Figure 5-6. ao/SampleClock and ao/StartTrigger68AO Sample Clock Timebase Signal68Getting Started with AO Applications in Software68Chapter 6 Digital Input and Output70I/O Protection70Programmable Power-Up States70Connecting Digital I/O Signals71Figure 6-1. NI 6232 Digital I/O Connections (DO Source)71Figure 6-2. NI 6233 Digital I/O Connections (DO Sink)72Logic Conventions72Table 6-1. NI 6232/6233 Logic Conventions73Getting Started with DIO Applications in Software73Chapter 7 Counters74Figure 7-1. M Series Counters75Counter Input Applications76Counting Edges76Single Point (On-Demand) Edge Counting76Figure 7-2. Single Point (On-Demand) Edge Counting76Figure 7-3. Single Point (On-Demand) Edge Counting with Pause Trigger77Buffered (Sample Clock) Edge Counting77Figure 7-4. Buffered (Sample Clock) Edge Counting77Non-Cumulative Buffered Edge Counting78Figure 7-5. Non-Cumulative Buffered Edge Counting78Controlling the Direction of Counting78Pulse-Width Measurement79Single Pulse-Width Measurement79Figure 7-6. Single Pulse-Width Measurement79Buffered Pulse-Width Measurement80Figure 7-7. Buffered Pulse-Width Measurement80Period Measurement80Single Period Measurement81Figure 7-8. Single Period Measurement81Buffered Period Measurement81Figure 7-9. Buffered Period Measurement82Semi-Period Measurement82Single Semi-Period Measurement82Buffered Semi-Period Measurement83Figure 7-10. Buffered Semi-Period Measurement83Frequency Measurement83Method 1-Measure Low Frequency with One Counter83Figure 7-11. Method 184Method 1b-Measure Low Frequency with One Counter (Averaged)84Figure 7-12. Method 1b85Method 2-Measure High Frequency with Two Counters85Figure 7-13. Method 286Method 3-Measure Large Range of Frequencies Using Two Counters86Figure 7-14. Method 387Choosing a Method for Measuring Frequency87Table 7-1. Frequency Measurement Method 188Table 7-2. Frequency Measurement Method Comparison89Position Measurement89Measurements Using Quadrature Encoders89Figure 7-15. X1 Encoding90Figure 7-16. X2 Encoding90Figure 7-17. X4 Encoding90Figure 7-18. Channel Z Reload with X4 Decoding91Measurements Using Two Pulse Encoders91Figure 7-19. Measurements Using Two Pulse Encoders91Two-Signal Edge-Separation Measurement92Single Two-Signal Edge-Separation Measurement92Figure 7-20. Single Two-Signal Edge-Separation Measurement93Buffered Two-Signal Edge-Separation Measurement93Figure 7-21. Buffered Two-Signal Edge-Separation Measurement93Counter Output Applications94Simple Pulse Generation94Single Pulse Generation94Figure 7-22. Single Pulse Generation94Single Pulse Generation with Start Trigger94Figure 7-23. Single Pulse Generation with Start Trigger95Retriggerable Single Pulse Generation95Figure 7-24. Retriggerable Single Pulse Generation95Pulse Train Generation96Continuous Pulse Train Generation96Figure 7-25. Continuous Pulse Train Generation96Frequency Generation97Using the Frequency Generator97Figure 7-26. Frequency Generator Block Diagram97Figure 7-27. Frequency Generator Output Waveform97Frequency Division98Pulse Generation for ETS98Figure 7-28. Pulse Generation for ETS99Counter Timing Signals99Counter n Source Signal100Table 7-3. Counter Applications and Counter n Source100Routing a Signal to Counter n Source100Routing Counter n Source to an Output Terminal101Counter n Gate Signal101Routing a Signal to Counter n Gate101Routing Counter n Gate to an Output Terminal101Counter n Aux Signal101Routing a Signal to Counter n Aux102Counter n A, Counter n B, and Counter n Z Signals102Routing Signals to A, B, and Z Counter Inputs102Routing Counter n Z Signal to an Output Terminal102Counter n Up_Down Signal102Counter n HW Arm Signal103Routing Signals to Counter n HW Arm Input103Counter n Internal Output and Counter n TC Signals103Routing Counter n Internal Output to an Output Terminal104Frequency Output Signal104Routing Frequency Output to a Terminal104Default Counter Terminals104Table 7-4. NI 6232/6233 Device Default NI-DAQmx Counter/Timer Pins104Counter Triggering105Arm Start Trigger105Start Trigger105Pause Trigger106Other Counter Features106Cascading Counters106Counter Filters106Table 7-5. Filters107Figure 7-29. Filter Example107Prescaling107Figure 7-30. Prescaling108Duplicate Count Prevention108Duplicate Count Prevention Example108Figure 7-31. Duplicate Count Prevention Example109Duplicate Count Example109Figure 7-32. Duplicate Count Example110Example Application That Prevents Duplicate Count110Figure 7-33. Duplicate Count Prevention Example110When To Use Duplicate Count Prevention111Enabling Duplicate Count Prevention in NI-DAQmx111Synchronization Modes111Table 7-6. Synchronization Mode Conditions11280 MHz Source Mode112Figure 7-34. 80 MHz Source Mode112Other Internal Source Mode113Figure 7-35. Other Internal Source Mode113External Source Mode113Figure 7-36. External Source Mode113Chapter 8 PFI114Figure 8-1. NI 6232/6233 PFI Input Circuitry114Figure 8-2. NI 6232/6233 PFI Output Circuitry115Using PFI Terminals as Timing Input Signals115Exporting Timing Output Signals Using PFI Terminals116Using PFI Terminals as Static Digital Inputs and Outputs116Connecting PFI Input Signals116Figure 8-3. PFI Input Signals Connections117PFI Filters117Table 8-1. Filters118Figure 8-4. Filter Example118I/O Protection118Programmable Power-Up States119Connecting Digital I/O Signals119Figure 8-5. NI 6232 Digital I/O Connections (DO Source)120Figure 8-6. NI 6233 Digital I/O Connections (DO Sink)121Chapter 9 Isolation and Digital Isolators122Table 9-1. Ground Symbols122Figure 9-1. General NI 6232/6233 Block Diagram122Digital Isolation123Benefits of an Isolated DAQ Device123Chapter 10 Digital Routing and Clock Generation124Clock Routing124Figure 10-1. M Series Clock Routing Circuitry12480 MHz Timebase12520 MHz Timebase125100 kHz Timebase125External Reference Clock12510 MHz Reference Clock126Synchronizing Multiple Devices126Real-Time System Integration Bus (RTSI)126RTSI Connector Pinout127Figure 10-2. NI 6232/6233 RTSI Pinout127Table 10-1. RTSI Signal Descriptions128Using RTSI as Outputs128Using RTSI Terminals as Timing Input Signals129RTSI Filters129Table 10-2. Filters130Figure 10-3. Filter Example130PXI Clock and Trigger Signals131PXI_CLK10131PXI Triggers131PXI_STAR Trigger131PXI_STAR Filters132Table 10-3. Filters132Figure 10-4. Filter Example133Chapter 11 Bus Interface134DMA Controllers134PXI Considerations135PXI Clock and Trigger Signals135PXI and PXI Express135Using PXI with CompactPCI136Data Transfer Methods136Direct Memory Access (DMA)136Interrupt Request (IRQ)137Programmed I/O137Changing Data Transfer Methods between DMA and IRQ137Chapter 12 Triggering138Triggering with a Digital Source138Figure 12-1. Falling-Edge Trigger138Appendix A Device-Specific Information140Figure A-1. NI 6232 Pinout141Table A-1. NI 6232 Device Default NI-DAQmx Counter/Timer Pins141Figure A-2. NI 6233 Pinout144Table A-2. NI 6233 Device Default NI-DAQmx Counter/Timer Pins144Appendix B Troubleshooting147Figure B-1. ai/SampleClock and ai/ConvertClock148Appendix C Technical Support and Professional Services150Glossary152Numbers/Symbols152A152B-C154D156E158F159G-I160K-M162N163O-P164Q165R-S166T168U-V169W170Index171Symbols171Numerics171A171B-C172D173E174F-I175K-N176O-R177S178T-U179V-X180文件大小: 3.0 MB页数: 180Language: English打开用户手册
用户手册目录NI 6232/6233 User Manual1Support2Worldwide Technical Support and Product Information2National Instruments Corporate Headquarters2Worldwide Offices2Important Information3Warranty3Copyright3Trademarks3Patents3WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS3Compliance5Contents6About This Manual13Conventions13Related Documentation14NI-DAQ14NI-DAQmx for Linux14NI-DAQmx Base15LabVIEW15LabWindows™/CVI™16Measurement Studio16ANSI C without NI Application Software16.NET Languages without NI Application Software16Device Documentation and Specifications17Training Courses17Technical Support on the Web17Chapter 1 Getting Started18Installing NI-DAQmx18Installing Other Software18Installing the Hardware18Device Pinouts18Device Specifications19Device Accessories and Cables19Chapter 2 DAQ System Overview20Figure 2-1. Components of a Typical DAQ System20DAQ Hardware20Figure 2-2. General NI 6232/6233 Block Diagram21DAQ-STC221Calibration Circuitry22Sensors and Transducers22Cables and Accessories23Custom Cabling23Programming Devices in Software24Chapter 3 Connector Information25I/O Connector Signal Descriptions25Table 3-1. I/O Connector Signals25RTSI Connector Pinout27Chapter 4 Analog Input28Figure 4-1. NI 6232/6233 Analog Input Circuitry28Analog Input Circuitry28Analog Input Range29Table 4-1. Input Ranges for NI 6232/623330Analog Input Ground-Reference Settings30Table 4-2. Analog Input Ground-Reference Settings31Figure 4-2. PGIA31Table 4-3. Signals Routed to the NI-PGIA32Configuring AI Ground-Reference Settings in Software32Figure 4-3. Enabling Multimode Scanning in LabVIEW33Multichannel Scanning Considerations33Use Low Impedance Sources33Use Short High-Quality Cabling34Carefully Choose the Channel Scanning Order34Avoid Switching from a Large to a Small Input Range34Insert Grounded Channel between Signal Channels35Minimize Voltage Step between Adjacent Channels35Avoid Scanning Faster Than Necessary36Example 136Example 236Analog Input Data Acquisition Methods36Software-Timed Acquisitions36Hardware-Timed Acquisitions37Buffered37Non-Buffered38Analog Input Triggering38Connecting Analog Voltage Input Signals38Table 4-4. Analog Input Configuration39Types of Signal Sources39Floating Signal Sources40Ground-Referenced Signal Sources40Differential Connection Considerations40Differential Connections for Ground-Referenced Signal Sources41Figure 4-4. Differential Connections for Ground-Referenced Signal Sources41Differential Input Biasing42Differential Connections for Non-Referenced or Floating Signal Sources42Figure 4-5. Differential Connections for Floating Signal Sources43Single-Ended Connection Considerations43Single-Ended Connections for Floating or Grounded Signal Sources44Figure 4-6. Single-Ended Connections for Floating Signal Sources (RSE Configuration)45Field Wiring Considerations45Analog Input Timing Signals46Figure 4-7. Analog Input Timing Options46Figure 4-8. Interval Sampling47Figure 4-9. Posttriggered Data Acquisition Example48Figure 4-10. Pretriggered Data Acquisition Example49AI Sample Clock Signal49Using an Internal Source50Using an External Source50Routing AI Sample Clock Signal to an Output Terminal50Other Timing Requirements50Figure 4-11. ai/SampleClock and ai/StartTrigger51AI Sample Clock Timebase Signal51AI Convert Clock Signal52Using an Internal Source52Using an External Source53Routing AI Convert Clock Signal to an Output Terminal53Using a Delay from Sample Clock to Convert Clock53Figure 4-12. ai/SampleClock and ai/ConvertClock53Other Timing Requirements54Figure 4-13. Single External Signal Driving ai/SampleClock and ai/ConvertClock Simultaneously54AI Convert Clock Timebase Signal54AI Hold Complete Event Signal55AI Start Trigger Signal55Using a Digital Source55Routing AI Start Trigger to an Output Terminal56AI Reference Trigger Signal56Figure 4-14. Reference Trigger Final Buffer57Using a Digital Source57Routing AI Reference Trigger Signal to an Output Terminal57AI Pause Trigger Signal57Using a Digital Source58Routing AI Pause Trigger Signal to an Output Terminal58Getting Started with AI Applications in Software58Chapter 5 Analog Output59Figure 5-1. NI 6232/6233 Analog Output Circuitry59Analog Output Circuitry59Minimizing Glitches on the Output Signal60Analog Output Data Generation Methods60Software-Timed Generations60Hardware-Timed Generations61Non-Buffered61Buffered61Analog Output Triggering62Connecting Analog Voltage Output Signals62Figure 5-2. Analog Output Connections63Analog Output Timing Signals63Figure 5-3. Analog Output Timing Options64AO Start Trigger Signal64Using a Digital Source64Routing AO Start Trigger Signal to an Output Terminal65AO Pause Trigger Signal65Figure 5-4. ao/PauseTrigger with the Onboard Clock Source65Figure 5-5. ao/PauseTrigger with Other Signal Source66Using a Digital Source66Routing AO Pause Trigger Signal to an Output Terminal66AO Sample Clock Signal66Using an Internal Source67Using an External Source67Routing AO Sample Clock Signal to an Output Terminal67Other Timing Requirements67Figure 5-6. ao/SampleClock and ao/StartTrigger68AO Sample Clock Timebase Signal68Getting Started with AO Applications in Software68Chapter 6 Digital Input and Output70I/O Protection70Programmable Power-Up States70Connecting Digital I/O Signals71Figure 6-1. NI 6232 Digital I/O Connections (DO Source)71Figure 6-2. NI 6233 Digital I/O Connections (DO Sink)72Logic Conventions72Table 6-1. NI 6232/6233 Logic Conventions73Getting Started with DIO Applications in Software73Chapter 7 Counters74Figure 7-1. M Series Counters75Counter Input Applications76Counting Edges76Single Point (On-Demand) Edge Counting76Figure 7-2. Single Point (On-Demand) Edge Counting76Figure 7-3. Single Point (On-Demand) Edge Counting with Pause Trigger77Buffered (Sample Clock) Edge Counting77Figure 7-4. Buffered (Sample Clock) Edge Counting77Non-Cumulative Buffered Edge Counting78Figure 7-5. Non-Cumulative Buffered Edge Counting78Controlling the Direction of Counting78Pulse-Width Measurement79Single Pulse-Width Measurement79Figure 7-6. Single Pulse-Width Measurement79Buffered Pulse-Width Measurement80Figure 7-7. Buffered Pulse-Width Measurement80Period Measurement80Single Period Measurement81Figure 7-8. Single Period Measurement81Buffered Period Measurement81Figure 7-9. Buffered Period Measurement82Semi-Period Measurement82Single Semi-Period Measurement82Buffered Semi-Period Measurement83Figure 7-10. Buffered Semi-Period Measurement83Frequency Measurement83Method 1-Measure Low Frequency with One Counter83Figure 7-11. Method 184Method 1b-Measure Low Frequency with One Counter (Averaged)84Figure 7-12. Method 1b85Method 2-Measure High Frequency with Two Counters85Figure 7-13. Method 286Method 3-Measure Large Range of Frequencies Using Two Counters86Figure 7-14. Method 387Choosing a Method for Measuring Frequency87Table 7-1. Frequency Measurement Method 188Table 7-2. Frequency Measurement Method Comparison89Position Measurement89Measurements Using Quadrature Encoders89Figure 7-15. X1 Encoding90Figure 7-16. X2 Encoding90Figure 7-17. X4 Encoding90Figure 7-18. Channel Z Reload with X4 Decoding91Measurements Using Two Pulse Encoders91Figure 7-19. Measurements Using Two Pulse Encoders91Two-Signal Edge-Separation Measurement92Single Two-Signal Edge-Separation Measurement92Figure 7-20. Single Two-Signal Edge-Separation Measurement93Buffered Two-Signal Edge-Separation Measurement93Figure 7-21. Buffered Two-Signal Edge-Separation Measurement93Counter Output Applications94Simple Pulse Generation94Single Pulse Generation94Figure 7-22. Single Pulse Generation94Single Pulse Generation with Start Trigger94Figure 7-23. Single Pulse Generation with Start Trigger95Retriggerable Single Pulse Generation95Figure 7-24. Retriggerable Single Pulse Generation95Pulse Train Generation96Continuous Pulse Train Generation96Figure 7-25. Continuous Pulse Train Generation96Frequency Generation97Using the Frequency Generator97Figure 7-26. Frequency Generator Block Diagram97Figure 7-27. Frequency Generator Output Waveform97Frequency Division98Pulse Generation for ETS98Figure 7-28. Pulse Generation for ETS99Counter Timing Signals99Counter n Source Signal100Table 7-3. Counter Applications and Counter n Source100Routing a Signal to Counter n Source100Routing Counter n Source to an Output Terminal101Counter n Gate Signal101Routing a Signal to Counter n Gate101Routing Counter n Gate to an Output Terminal101Counter n Aux Signal101Routing a Signal to Counter n Aux102Counter n A, Counter n B, and Counter n Z Signals102Routing Signals to A, B, and Z Counter Inputs102Routing Counter n Z Signal to an Output Terminal102Counter n Up_Down Signal102Counter n HW Arm Signal103Routing Signals to Counter n HW Arm Input103Counter n Internal Output and Counter n TC Signals103Routing Counter n Internal Output to an Output Terminal104Frequency Output Signal104Routing Frequency Output to a Terminal104Default Counter Terminals104Table 7-4. NI 6232/6233 Device Default NI-DAQmx Counter/Timer Pins104Counter Triggering105Arm Start Trigger105Start Trigger105Pause Trigger106Other Counter Features106Cascading Counters106Counter Filters106Table 7-5. Filters107Figure 7-29. Filter Example107Prescaling107Figure 7-30. Prescaling108Duplicate Count Prevention108Duplicate Count Prevention Example108Figure 7-31. Duplicate Count Prevention Example109Duplicate Count Example109Figure 7-32. Duplicate Count Example110Example Application That Prevents Duplicate Count110Figure 7-33. Duplicate Count Prevention Example110When To Use Duplicate Count Prevention111Enabling Duplicate Count Prevention in NI-DAQmx111Synchronization Modes111Table 7-6. Synchronization Mode Conditions11280 MHz Source Mode112Figure 7-34. 80 MHz Source Mode112Other Internal Source Mode113Figure 7-35. Other Internal Source Mode113External Source Mode113Figure 7-36. External Source Mode113Chapter 8 PFI114Figure 8-1. NI 6232/6233 PFI Input Circuitry114Figure 8-2. NI 6232/6233 PFI Output Circuitry115Using PFI Terminals as Timing Input Signals115Exporting Timing Output Signals Using PFI Terminals116Using PFI Terminals as Static Digital Inputs and Outputs116Connecting PFI Input Signals116Figure 8-3. PFI Input Signals Connections117PFI Filters117Table 8-1. Filters118Figure 8-4. Filter Example118I/O Protection118Programmable Power-Up States119Connecting Digital I/O Signals119Figure 8-5. NI 6232 Digital I/O Connections (DO Source)120Figure 8-6. NI 6233 Digital I/O Connections (DO Sink)121Chapter 9 Isolation and Digital Isolators122Table 9-1. Ground Symbols122Figure 9-1. General NI 6232/6233 Block Diagram122Digital Isolation123Benefits of an Isolated DAQ Device123Chapter 10 Digital Routing and Clock Generation124Clock Routing124Figure 10-1. M Series Clock Routing Circuitry12480 MHz Timebase12520 MHz Timebase125100 kHz Timebase125External Reference Clock12510 MHz Reference Clock126Synchronizing Multiple Devices126Real-Time System Integration Bus (RTSI)126RTSI Connector Pinout127Figure 10-2. NI 6232/6233 RTSI Pinout127Table 10-1. RTSI Signal Descriptions128Using RTSI as Outputs128Using RTSI Terminals as Timing Input Signals129RTSI Filters129Table 10-2. Filters130Figure 10-3. Filter Example130PXI Clock and Trigger Signals131PXI_CLK10131PXI Triggers131PXI_STAR Trigger131PXI_STAR Filters132Table 10-3. Filters132Figure 10-4. Filter Example133Chapter 11 Bus Interface134DMA Controllers134PXI Considerations135PXI Clock and Trigger Signals135PXI and PXI Express135Using PXI with CompactPCI136Data Transfer Methods136Direct Memory Access (DMA)136Interrupt Request (IRQ)137Programmed I/O137Changing Data Transfer Methods between DMA and IRQ137Chapter 12 Triggering138Triggering with a Digital Source138Figure 12-1. Falling-Edge Trigger138Appendix A Device-Specific Information140Figure A-1. NI 6232 Pinout141Table A-1. NI 6232 Device Default NI-DAQmx Counter/Timer Pins141Figure A-2. NI 6233 Pinout144Table A-2. NI 6233 Device Default NI-DAQmx Counter/Timer Pins144Appendix B Troubleshooting147Figure B-1. ai/SampleClock and ai/ConvertClock148Appendix C Technical Support and Professional Services150Glossary152Numbers/Symbols152A152B-C154D156E158F159G-I160K-M162N163O-P164Q165R-S166T168U-V169W170Index171Symbols171Numerics171A171B-C172D173E174F-I175K-N176O-R177S178T-U179V-X180文件大小: 3.0 MB页数: 180Language: English打开用户手册