用户手册目录Cover1Cautions4General Precautions on Handling of Product5Configuration of This Manual6Preface7List of Items Revised or Added for This Version9Contents17Figures31Tables39Section 1 Overview and Pin Functions451.1 SH7709S Features451.2 Block Diagram501.3 Pin Description511.3.1 Pin Assignment511.3.2 Pin Function53Section 2 CPU632.1 Register Configuration632.1.1 Privileged Mode and Banks632.1.2 General Registers662.1.3 System Registers672.1.4 Control Registers672.2 Data Formats692.2.1 Data Format in Registers692.2.2 Data Format in Memory692.3 Instruction Features702.3.1 Execution Environment702.3.2 Addressing Modes722.3.3 Instruction Formats762.4 Instruction Set792.4.1 Instruction Set Classified by Function792.4.2 Instruction Code Map942.5 Processor States and Processor Modes972.5.1 Processor States972.5.2 Processor Modes98Section 3 Memory Management Unit (MMU)993.1 Overview993.1.1 Features993.1.2 Role of MMU993.1.3 SH7709S MMU1023.1.4 Register Configuration1053.2 Register Description1053.3 TLB Functions1073.3.1 Configuration of the TLB1073.3.2 TLB Indexing1093.3.3 TLB Address Comparison1103.3.4 Page Management Information1123.4 MMU Functions1133.4.1 MMU Hardware Management1133.4.2 MMU Software Management1133.4.3 MMU Instruction (LDTLB)1143.4.4 Avoiding Synonym Problems1163.5 MMU Exceptions1183.5.1 TLB Miss Exception1183.5.2 TLB Protection Violation Exception1193.5.3 TLB Invalid Exception1203.5.4 Initial Page Write Exception1213.5.5 Processing Flow in Event of MMU Exception (Same Processing Flow for Address Error)1233.6 Configuration of Memory-Mapped TLB1243.6.1 Address Array1243.6.2 Data Array1253.6.3 Usage Examples1273.7 Usage Note127Section 4 Exception Handling1294.1 Overview1294.1.1 Features1294.1.2 Register Configuration1294.2 Exception Handling Function1294.2.1 Exception Handling Flow1294.2.2 Exception Vector Addresses1304.2.3 Acceptance of Exceptions1324.2.4 Exception Codes1344.2.5 Exception Request Masks1354.2.6 Returning from Exception Handling1354.3 Register Descriptions1364.4 Exception Handling Operation1374.4.1 Reset1374.4.2 Interrupts1374.4.3 General Exceptions1384.5 Individual Exception Operations1384.5.1 Resets1384.5.2 General Exceptions1394.5.3 Interrupts1434.6 Cautions144Section 5 Cache1475.1 Overview1475.1.1 Features1475.1.2 Cache Structure1475.1.3 Register Configuration1495.2 Register Description1495.2.1 Cache Control Register (CCR)1495.2.2 Cache Control Register 2 (CCR2)1505.3 Cache Operation1535.3.1 Searching the Cache1535.3.2 Read Access1555.3.3 Prefetch Operation1555.3.4 Write Access1555.3.5 Write-Back Buffer1555.3.6 Coherency of Cache and External Memory1565.4 Memory-Mapped Cache1565.4.1 Address Array1565.4.2 Data Array1575.4.3 Examples of Usage159Section 6 Interrupt Controller (INTC)1616.1 Overview1616.1.1 Features1616.1.2 Block Diagram1626.1.3 Pin Configuration1636.1.4 Register Configuration1646.2 Interrupt Sources1656.2.1 NMI Interrupt1656.2.2 IRQ Interrupts1656.2.3 IRL Interrupts1666.2.4 PINT Interrupts1686.2.5 On-Chip Peripheral Module Interrupts1686.2.6 Interrupt Exception Handling and Priority1696.3 INTC Registers1756.3.1 Interrupt Priority Registers A to E (IPRA-IPRE)1756.3.2 Interrupt Control Register 0 (ICR0)1766.3.3 Interrupt Control Register 1 (ICR1)1776.3.4 Interrupt Control Register 2 (ICR2)1806.3.5 PINT Interrupt Enable Register (PINTER)1816.3.6 Interrupt Request Register 0 (IRR0)1826.3.7 Interrupt Request Register 1 (IRR1)1846.3.8 Interrupt Request Register 2 (IRR2)1856.4 INTC Operation1876.4.1 Interrupt Sequence1876.4.2 Multiple Interrupts1896.5 Interrupt Response Time189Section 7 User Break Controller1937.1 Overview1937.1.1 Features1937.1.2 Block Diagram1947.1.3 Register Configuration1957.2 Register Descriptions1967.2.1 Break Address Register A (BARA)1967.2.2 Break Address Mask Register A (BAMRA)1977.2.3 Break Bus Cycle Register A (BBRA)1987.2.4 Break Address Register B (BARB)2007.2.5 Break Address Mask Register B (BAMRB)2017.2.6 Break Data Register B (BDRB)2027.2.7 Break Data Mask Register B (BDMRB)2037.2.8 Break Bus Cycle Register B (BBRB)2047.2.9 Break Control Register (BRCR)2067.2.10 Execution Times Break Register (BETR)2107.2.11 Branch Source Register (BRSR)2117.2.12 Branch Destination Register (BRDR)2127.2.13 Break ASID Register A (BASRA)2137.2.14 Break ASID Register B (BASRB)2137.3 Operation Description2147.3.1 Flow of the User Break Operation2147.3.2 Break on Instruction Fetch Cycle2147.3.3 Break by Data Access Cycle2157.3.4 Sequential Break2167.3.5 Value of Saved Program Counter2167.3.6 PC Trace2177.3.7 Usage Examples2187.3.8 Notes223Section 8 Power-Down Modes2258.1 Overview2258.1.1 Power-Down Modes2258.1.2 Pin Configuration2278.1.3 Register Configuration2278.2 Register Descriptions2278.2.1 Standby Control Register (STBCR)2278.2.2 Standby Control Register 2 (STBCR2)2298.3 Sleep Mode2318.3.1 Transition to Sleep Mode2318.3.2 Canceling Sleep Mode2318.3.3 Precautions when Using the Sleep Mode2318.4 Standby Mode2328.4.1 Transition to Standby Mode2328.4.2 Canceling Standby Mode2338.4.3 Clock Pause Function2348.5 Module Standby Function2358.5.1 Transition to Module Standby Function2358.5.2 Clearing Module Standby Function2358.6 Timing of STATUS Pin Changes2368.6.1 Timing for Resets2368.6.2 Timing for Canceling Standby2388.6.3 Timing for Canceling Sleep Mode2408.7 Hardware Standby Mode2438.7.1 Transition to Hardware Standby Mode2438.7.2 Canceling Hardware Standby Mode2438.7.3 Hardware Standby Mode Timing244Section 9 On-Chip Oscillation Circuits2479.1 Overview2479.1.1 Features2479.2 Overview of CPG2489.2.1 CPG Block Diagram2489.2.2 CPG Pin Configuration2509.2.3 CPG Register Configuration2509.3 Clock Operating Modes2519.4 Register Descriptions2559.4.1 Frequency Control Register (FRQCR)2559.5 Changing the Frequency2579.5.1 Changing the Multiplication Rate2579.5.2 Changing the Division Ratio2579.6 Overview of WDT2589.6.1 Block Diagram of WDT2589.6.2 Register Configuration2589.7 WDT Registers2599.7.1 Watchdog Timer Counter (WTCNT)2599.7.2 Watchdog Timer Control/Status Register (WTCSR)2599.7.3 Notes on Register Access2619.8 Using the WDT2629.8.1 Canceling Standby2629.8.2 Changing the Frequency2629.8.3 Using Watchdog Timer Mode2639.8.4 Using Interval Timer Mode2639.9 Notes on Board Design264Section 10 Bus State Controller (BSC)26710.1 Overview26710.1.1 Features26710.1.2 Block Diagram26910.1.3 Pin Configuration27010.1.4 Register Configuration27210.1.5 Area Overview27310.1.6 PCMCIA Support27610.2 BSC Registers27910.2.1 Bus Control Register 1 (BCR1)27910.2.2 Bus Control Register 2 (BCR2)28310.2.3 Wait State Control Register 1 (WCR1)28410.2.4 Wait State Control Register 2 (WCR2)28510.2.5 Individual Memory Control Register (MCR)28910.2.6 PCMCIA Control Register (PCR)29210.2.7 Synchronous DRAM Mode Register (SDMR)29610.2.8 Refresh Timer Control/Status Register (RTCSR)29710.2.9 Refresh Timer Counter (RTCNT)29910.2.10 Refresh Time Constant Register (RTCOR)30010.2.11 Refresh Count Register (RFCR)30010.2.12 Cautions on Accessing Refresh Control Related Registers30110.2.13 MCS0 Control Register (MCSCR0)30210.2.14 MCS1 Control Register (MCSCR1)30310.2.15 MCS2 Control Register (MCSCR2)30310.2.16 MCS3 Control Register (MCSCR3)30310.2.17 MCS4 Control Register (MCSCR4)30310.2.18 MCS5 Control Register (MCSCR5)30310.2.19 MCS6 Control Register (MCSCR6)30310.2.20 MCS7 Control Register (MCSCR7)30310.3 BSC Operation30410.3.1 Endian/Access Size and Data Alignment30410.3.2 Description of Areas30910.3.3 Basic Interface31210.3.4 Synchronous DRAM Interface32010.3.5 Burst ROM Interface34810.3.6 PCMCIA Interface35110.3.7 Waits between Access Cycles36310.3.8 Bus Arbitration36410.3.9 Bus Pull-Up36510.3.10 MCS[0] to MCS[7] Pin Control367Section 11 Direct Memory Access Controller (DMAC)37111.1 Overview37111.1.1 Features37111.1.2 Block Diagram37311.1.3 Pin Configuration37411.1.4 Register Configuration37511.2 Register Descriptions37711.2.1 DMA Source Address Registers 0-3 (SAR0-SAR3)37711.2.2 DMA Destination Address Registers 0-3 (DAR0-DAR3)37811.2.3 DMA Transfer Count Registers 0-3 (DMATCR0-DMATCR3)37911.2.4 DMA Channel Control Registers 0-3 (CHCR0-CHCR3)38011.2.5 DMA Operation Register (DMAOR)38711.3 Operation38911.3.1 DMA Transfer Flow38911.3.2 DMA Transfer Requests39111.3.3 Channel Priority39311.3.4 DMA Transfer Types39611.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing40711.3.6 Source Address Reload Function41611.3.7 DMA Transfer Ending Conditions41811.4 Compare Match Timer (CMT)42011.4.1 Overview42011.4.2 Register Descriptions42111.4.3 Operation42411.4.4 Compare Match42511.5 Examples of Use42711.5.1 Example of DMA Transfer between On-Chip IrDA and External Memory42711.5.2 Example of DMA Transfer between A/D Converter and External Memory42811.5.3 Example of DMA Transfer between External Memory and SCIF Transmitter (Indirect Address On)42911.6 Usage Notes431Section 12 Timer (TMU)43312.1 Overview43312.1.1 Features43312.1.2 Block Diagram43412.1.3 Pin Configuration43512.1.4 Register Configuration43512.2 TMU Registers43612.2.1 Timer Output Control Register (TOCR)43612.2.2 Timer Start Register (TSTR)43612.2.3 Timer Control Registers (TCR)43712.2.4 Timer Constant Registers (TCOR)44112.2.5 Timer Counters (TCNT)44112.2.6 Input Capture Register (TCPR2)44312.3 TMU Operation44412.3.1 General Operation44412.3.2 Input Capture Function44712.4 Interrupts44812.4.1 Status Flag Setting Timing44812.4.2 Status Flag Clearing Timing44912.4.3 Interrupt Sources and Priorities44912.5 Usage Notes45012.5.1 Writing to Registers45012.5.2 Reading Registers450Section 13 Realtime Clock (RTC)45113.1 Overview45113.1.1 Features45113.1.2 Block Diagram45213.1.3 Pin Configuration45313.1.4 RTC Register Configuration45413.2 RTC Registers45513.2.1 64-Hz Counter (R64CNT)45513.2.2 Second Counter (RSECCNT)45513.2.3 Minute Counter (RMINCNT)45613.2.4 Hour Counter (RHRCNT)45613.2.5 Day of Week Counter (RWKCNT)45713.2.6 Date Counter (RDAYCNT)45813.2.7 Month Counter (RMONCNT)45813.2.8 Year Counter (RYRCNT)45913.2.9 Second Alarm Register (RSECAR)45913.2.10 Minute Alarm Register (RMINAR)46013.2.11 Hour Alarm Register (RHRAR)46013.2.12 Day of Week Alarm Register (RWKAR)46113.2.13 Date Alarm Register (RDAYAR)46213.2.14 Month Alarm Register (RMONAR)46213.2.15 RTC Control Register 1 (RCR1)46313.2.16 RTC Control Register 2 (RCR2)46413.3 RTC Operation46613.3.1 Initial Settings of Registers after Power-On46613.3.2 Setting the Time46613.3.3 Reading the Time46713.3.4 Alarm Function46813.3.5 Crystal Oscillator Circuit46913.4 Usage Notes47013.4.1 Register Writing during RTC Count47013.4.2 Use of Realtime Clock (RTC) Periodic Interrupts47013.4.3 Precautions when Using RTC Module Standby470Section 14 Serial Communication Interface (SCI)47114.1 Overview47114.1.1 Features47114.1.2 Block Diagram47214.1.3 Pin Configuration47514.1.4 Register Configuration47614.2 Register Descriptions47614.2.1 Receive Shift Register (SCRSR)47614.2.2 Receive Data Register (SCRDR)47714.2.3 Transmit Shift Register (SCTSR)47714.2.4 Transmit Data Register (SCTDR)47814.2.5 Serial Mode Register (SCSMR)47814.2.6 Serial Control Register (SCSCR)48114.2.7 Serial Status Register (SCSSR)48414.2.8 SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR)48814.2.9 Bit Rate Register (SCBRR)49014.3 Operation49714.3.1 Overview49714.3.2 Operation in Asynchronous Mode49914.3.3 Multiprocessor Communication50914.3.4 Synchronous Operation51814.4 SCI Interrupts52814.5 Usage Notes529Section 15 Smart Card Interface53315.1 Overview53315.1.1 Features53315.1.2 Block Diagram53415.1.3 Pin Configuration53515.1.4 Smart Card Interface Registers53515.2 Register Descriptions53615.2.1 Smart Card Mode Register (SCSCMR)53615.2.2 Serial Status Register (SCSSR)53715.3 Operation53815.3.1 Overview53815.3.2 Pin Connections53915.3.3 Data Format54015.3.4 Register Settings54115.3.5 Clock54215.3.6 Data Transmission and Reception54515.4 Usage Notes55115.4.1 Receive Data Timing and Receive Margin in Asynchronous Mode55115.4.2 Retransmission (Receive and Transmit Modes)553Section 16 Serial Communication Interface with FIFO (SCIF)55516.1 Overview55516.1.1 Features55516.1.2 Block Diagram55616.1.3 Pin Configuration55916.1.4 Register Configuration56016.2 Register Descriptions56116.2.1 Receive Shift Register (SCRSR)56116.2.2 Receive FIFO Data Register (SCFRDR)56116.2.3 Transmit Shift Register (SCTSR)56116.2.4 Transmit FIFO Data Register (SCFTDR)56216.2.5 Serial Mode Register (SCSMR)56216.2.6 Serial Control Register (SCSCR)56416.2.7 Serial Status Register (SCSSR)56616.2.8 Bit Rate Register (SCBRR)57116.2.9 FIFO Control Register (SCFCR)57816.2.10 FIFO Data Count Register (SCFDR)58016.3 Operation58116.3.1 Overview58116.3.2 Serial Operation58216.4 SCIF Interrupts59416.5 Usage Notes595Section 17 IrDA59917.1 Overview59917.1.1 Features59917.1.2 Block Diagram60017.1.3 Pin Configuration60317.1.4 Register Configuration60417.2 Register Description60517.2.1 Serial Mode Register (SCSMR)60517.3 Operation Description60717.3.1 Overview60717.3.2 Transmitting60717.3.3 Receiving608Section 18 Pin Function Controller60918.1 Overview60918.2 Register Configuration61318.3 Register Descriptions61418.3.1 Port A Control Register (PACR)61418.3.2 Port B Control Register (PBCR)61518.3.3 Port C Control Register (PCCR)61618.3.4 Port D Control Register (PDCR)61718.3.5 Port E Control Register (PECR)61818.3.6 Port F Control Register (PFCR)61918.3.7 Port G Control Register (PGCR)62018.3.8 Port H Control Register (PHCR)62118.3.9 Port J Control Register (PJCR)62318.3.10 Port K Control Register (PKCR)62418.3.11 Port L Control Register (PLCR)62518.3.12 SC Port Control Register (SCPCR)626Section 19 I/O Ports63119.1 Overview63119.2 Port A63119.2.1 Register Description63119.2.2 Port A Data Register (PADR)63219.3 Port B63319.3.1 Register Description63319.3.2 Port B Data Register (PBDR)63419.4 Port C63519.4.1 Register Description63519.4.2 Port C Data Register (PCDR)63619.5 Port D63719.5.1 Register Description63719.5.2 Port D Data Register (PDDR)63819.6 Port E63919.6.1 Register Description63919.6.2 Port E Data Register (PEDR)64019.7 Port F64119.7.1 Register Description64119.7.2 Port F Data Register (PFDR)64219.8 Port G64319.8.1 Register Description64319.8.2 Port G Data Register (PGDR)64419.9 Port H64519.9.1 Register Description64519.9.2 Port H Data Register (PHDR)64619.10 Port J64719.10.1 Register Description64719.10.2 Port J Data Register (PJDR)64819.11 Port K64919.11.1 Register Description64919.11.2 Port K Data Register (PKDR)65019.12 Port L65119.12.1 Register Description65119.12.2 Port L Data Register (PLDR)65219.13 SC Port65319.13.1 Register Description65319.13.2 SC Port Data Register (SCPDR)654Section 20 A/D Converter65720.1 Overview65720.1.1 Features65720.1.2 Block Diagram65820.1.3 Input Pins65920.1.4 Register Configuration66020.2 Register Descriptions66120.2.1 A/D Data Registers A to D (ADDRA to ADDRD)66120.2.2 A/D Control/Status Register (ADCSR)66220.2.3 A/D Control Register (ADCR)66520.3 Bus Master Interface66620.4 Operation66720.4.1 Single Mode (MULTI = 0)66720.4.2 Multi Mode (MULTI = 1, SCN = 0)66920.4.3 Scan Mode (MULTI = 1, SCN = 1)67120.4.4 Input Sampling and A/D Conversion Time67320.4.5 External Trigger Input Timing67420.5 Interrupts67520.6 Definitions of A/D Conversion Accuracy67520.7 Usage Notes67620.7.1 Setting Analog Input Voltage67620.7.2 Processing of Analog Input Pins67620.7.3 Access Size and Read Data677Section 21 D/A Converter67921.1 Overview67921.1.1 Features67921.1.2 Block Diagram67921.1.3 I/O Pins68021.1.4 Register Configuration68021.2 Register Descriptions68121.2.1 D/A Data Registers 0 and 1 (DADR0/1)68121.2.2 D/A Control Register (DACR)68121.3 Operation683Section 22 User Debugging Interface (UDI)68522.1 Overview68522.2 User Debugging Interface (UDI)68522.2.1 Pin Descriptions68522.2.2 Block Diagram68622.3 Register Descriptions68622.3.1 Bypass Register (SDBPR)68722.3.2 Instruction Register (SDIR)68722.3.3 Boundary Scan Register (SDBSR)68822.4 UDI Operation69522.4.1 TAP Controller69522.4.2 Reset Configuration69622.4.3 UDI Reset69722.4.4 UDI Interrupt69722.4.5 Bypass69722.4.6 Using UDI to Recover from Sleep Mode69722.5 Boundary Scan69822.5.1 Supported Instructions69822.5.2 Points for Attention69922.6 Usage Notes69922.7 Advanced User Debugger (AUD)699Section 23 Electrical Characteristics70123.1 Absolute Maximum Ratings70123.2 DC Characteristics70323.3 AC Characteristics70723.3.1 Clock Timing70823.3.2 Control Signal Timing71423.3.3 AC Bus Timing71723.3.4 Basic Timing71923.3.5 Burst ROM Timing72223.3.6 Synchronous DRAM Timing72523.3.7 PCMCIA Timing74323.3.8 Peripheral Module Signal Timing75023.3.9 UDI-Related Pin Timing75323.3.10 AC Characteristics Measurement Conditions75523.3.11 Delay Time Variation Due to Load Capacitance75623.4 A/D Converter Characteristics75723.5 D/A Converter Characteristics757Appendix A Pin Functions759A.1 Pin States759A.2 Pin Specifications763A.3 Treatment of Unused Pins768A.4 Pin States in Access to Each Address Space769Appendix B Memory-Mapped Control Registers783B.1 Register Address Map783B.2 Register Bits789Appendix C Product Lineup801Appendix D Package Dimensions802Colophon805Address List806Back Cover807文件大小： 4.4 MB页数： 807Language: English打开用户手册
