用户手册 — Texas Instruments 180 to 100 Pin DIMM Adapter TMDSADAP180TO100

目录

• 1 Device Summary

  1
  • 1.1 Features

    1
  • 1.2 Applications

    2
  • 1.3 Description

    2
  • 1.4 Functional Block Diagram

    3
• Table of Contents

  4
• 2 Revision History

  5
• 3 Device Overview

  6
  • 3.1 Device Characteristics

    7
  • 3.2 Memory Maps

    10
    • 3.2.1 Control Subsystem Memory Map

      10
    • 3.2.2 Master Subsystem Memory Map

      15
  • 3.3 Master Subsystem

    21
    • 3.3.1 Cortex-M3 CPU

      21
    • 3.3.2 Cortex-M3 DMA and NVIC

      23
    • 3.3.3 Cortex-M3 Interrupts

      23
    • 3.3.4 Cortex-M3 Vector Table

      26
    • 3.3.5 Cortex-M3 Local Peripherals

      26
    • 3.3.6 Cortex-M3 Local Memory

      26
    • 3.3.7 Cortex-M3 Accessing Shared Resources and Analog Peripherals

      27
  • 3.4 Control Subsystem

    27
    • 3.4.1 C28x CPU/FPU/VCU

      29
    • 3.4.2 C28x Core Hardware Built-In Self-Test

      29
    • 3.4.3 C28x Peripheral Interrupt Expansion

      29
    • 3.4.4 C28x Direct Memory Access

      30
    • 3.4.5 C28x Local Peripherals

      31
    • 3.4.6 C28x Local Memory

      31
    • 3.4.7 C28x Accessing Shared Resources and Analog Peripherals

      31
  • 3.5 Analog Subsystem

    32
    • 3.5.1 ADC1

      32
    • 3.5.2 ADC2

      32
    • 3.5.3 Analog Comparator + DAC

      34
    • 3.5.4 Analog Common Interface Bus

      34
  • 3.6 Master Subsystem NMIs

    35
  • 3.7 Control Subsystem NMIs

    35
  • 3.8 Resets

    37
    • 3.8.1 Cortex-M3 Resets

      37
    • 3.8.2 C28x Resets

      39
    • 3.8.3 Analog Subsystem and Shared Resources Resets

      39
    • 3.8.4 Device Boot Sequence

      39
  • 3.9 Internal Voltage Regulation and Power-On-Reset Functionality

    42
    • 3.9.1 Analog Subsystem's Internal 1.8-V VREG

      42
    • 3.9.2 Digital Subsystem's Internal 1.2-V VREG

      44
    • 3.9.3 Analog and Digital Subsystems' Power-On-Reset Functionality

      44
    • 3.9.4 Connecting ARS and XRS Pins

      44
  • 3.10 Input Clocks and PLLs

    45
    • 3.10.1 Internal Oscillator (Zero-Pin)

      45
    • 3.10.2 Crystal Oscillator/Resonator (Pins X1/X2 and VSSOSC)

      46
    • 3.10.3 External Oscillators (Pins X1, VSSOSC, XCLKIN)

      46
    • 3.10.4 Main PLL

      46
    • 3.10.5 USB PLL

      51
  • 3.11 Master Subsystem Clocking

    55
    • 3.11.1 Cortex-M3 Run Mode

      58
    • 3.11.2 Cortex-M3 Sleep Mode

      58
    • 3.11.3 Cortex-M3 Deep Sleep Mode

      59
  • 3.12 Control Subsystem Clocking

    60
    • 3.12.1 C28x Normal Mode

      60
    • 3.12.2 C28x IDLE Mode

      60
    • 3.12.3 C28x STANDBY Mode

      62
  • 3.13 Analog Subsystem Clocking

    63
  • 3.14 Shared Resources Clocking

    63
  • 3.15 Loss of Input Clock (NMI Watchdog Function)

    63
  • 3.16 GPIOs and Other Pins

    65
    • 3.16.1 GPIO_MUX1

      65
    • 3.16.2 GPIO_MUX2

      81
    • 3.16.3 AIO_MUX1

      83
    • 3.16.4 AIO_MUX2

      84
  • 3.17 Emulation/JTAG

    85
  • 3.18 Code Security Module

    88
    • 3.18.1 Functional Description

      88
  • 3.19 µCRC Module

    89
    • 3.19.1 Functional Description

      89
    • 3.19.2 CRC Polynomials

      89
    • 3.19.3 CRC Calculation Procedure

      89
    • 3.19.4 CRC Calculation for Data Stored In Secure Memory

      90
• 4 Terminal Description

  91
  • 4.1 Terminal Assignments

    91
  • 4.2 Terminal Functions

    96
• 5 Device Operating Conditions

  123
  • 5.1 Absolute Maximum Ratings

    123
  • 5.2 Handling Ratings

    123
  • 5.3 Recommended Operating Conditions

    124
  • 5.4 Electrical Characteristics

    125
• 6 Electrical Specifications

  126
  • 6.1 Current Consumption

    126
  • 6.2 Thermal Design Considerations

    130
  • 6.3 Timing Parameter Symbology

    131
    • 6.3.1 General Notes on Timing Parameters

      131
    • 6.3.2 Test Load Circuit

      131
  • 6.4 Clock Frequencies, Requirements, and Characteristics

    132
    • 6.4.1 Input Clock Frequency and Timing Requirements, PLL Lock Times

      132
    • 6.4.2 Internal Clock Frequencies

      133
    • 6.4.3 Output Clock Frequency and Switching Characteristics

      134
  • 6.5 Power Sequencing

    135
    • 6.5.1 Changing the Frequency of the Main PLL

      137
    • 6.5.2 Power Management and Supervisory Circuit Solutions

      138
  • 6.6 Flash Timing – Master Subsystem

    139
  • 6.7 Flash Timing – Control Subsystem

    142
  • 6.8 GPIO Electrical Data and Timing

    145
    • 6.8.1  GPIO - Output Timing

      145
    • 6.8.2  GPIO - Input Timing

      146
    • 6.8.3 Sampling Window Width for Input Signals

      147
    • 6.8.4 Low-Power Mode Wakeup Timing

      148
  • 6.9 External Interrupt Electrical Data and Timing

    153
• 7 Peripheral Information and Timings

  154
  • 7.1 Analog and Shared Peripherals

    154
    • 7.1.1 Analog-to-Digital Converter

      154
      • 7.1.1.1 Sample Mode

        154
      • 7.1.1.2 Start-of-Conversion Triggers

        156
      • 7.1.1.3 Analog Inputs

        156
      • 7.1.1.4 ADC Result Registers and EOC Interrupts

        156
      • 7.1.1.5 ADC Electrical Data and Timing

        157
    • 7.1.2 Comparator + DAC Units

      158
      • 7.1.2.1 On-Chip Comparator and DAC Electrical Data and Timing

        160
    • 7.1.3 Interprocessor Communications

      161
    • 7.1.4 External Peripheral Interface

      163
      • 7.1.4.1 EPI General-Purpose Mode

        165
      • 7.1.4.2 EPI SDRAM Mode

        168
      • 7.1.4.3 EPI Host Bus Mode

        170
      • 7.1.4.4 EPI Electrical Data and Timing

        184
  • 7.2 Master Subsystem Peripherals

    190
    • 7.2.1 Synchronous Serial Interface

      190
      • 7.2.1.1 Bit Rate Generation

        190
      • 7.2.1.2 Transmit FIFO

        192
      • 7.2.1.3 Receive FIFO

        192
      • 7.2.1.4 Interrupts

        192
      • 7.2.1.5 Frame Formats

        193
    • 7.2.2 Universal Asynchronous Receiver/Transmitter

      194
      • 7.2.2.1 Baud-Rate Generation

        194
      • 7.2.2.2 Transmit and Receive Logic

        196
      • 7.2.2.3 Data Transmission and Reception

        196
      • 7.2.2.4 Interrupts

        197
    • 7.2.3 Cortex-M3 Inter-Integrated Circuit

      198
      • 7.2.3.1 Functional Overview

        198
      • 7.2.3.2 Available Speed Modes

        198
      • 7.2.3.3 I2C Electrical Data and Timing

        200
    • 7.2.4 Cortex-M3 Controller Area Network

      201
      • 7.2.4.1 Functional Overview

        201
    • 7.2.5 Cortex-M3 Universal Serial Bus Controller

      203
      • 7.2.5.1 Functional Description

        203
    • 7.2.6 Cortex-M3 Ethernet Media Access Controller

      205
      • 7.2.6.1 Functional Overview

        205
      • 7.2.6.2 MII Signals

        207
      • 7.2.6.3 EMAC Electrical Data and Timing

        208
      • 7.2.6.4 MDIO Electrical Data and Timing

        210
  • 7.3 Control Subsystem Peripherals

    211
    • 7.3.1 High-Resolution PWM and Enhanced PWM Modules

      211
      • 7.3.1.1 HRPWM Electrical Data and Timing

        214
      • 7.3.1.2 ePWM Electrical Data and Timing

        214
    • 7.3.2 Enhanced Capture Module

      216
      • 7.3.2.1 eCAP Electrical Data and Timing

        216
    • 7.3.3 Enhanced Quadrature Encoder Pulse Module

      218
      • 7.3.3.1 eQEP Electrical Data and Timing

        218
    • 7.3.4 C28x Inter-Integrated Circuit Module

      220
      • 7.3.4.1 Functional Overview

        222
      • 7.3.4.2 Clock Generation

        222
      • 7.3.4.3 I2C Electrical Data and Timing

        222
    • 7.3.5 C28x Serial Communications Interface

      223
      • 7.3.5.1 Architecture

        225
      • 7.3.5.2 Multiprocessor and Asynchronous Communication Modes

        225
    • 7.3.6 C28x Serial Peripheral Interface

      226
      • 7.3.6.1 Functional Overview

        228
      • 7.3.6.2 SPI Electrical Data and Timing

        228
    • 7.3.7 C28x Multichannel Buffered Serial Port

      236
      • 7.3.7.1 McBSP Electrical Data and Timing

        239
• 8 Device and Documentation Support

  246
  • 8.1 Device Support

    246
    • 8.1.1 Development Support

      246
    • 8.1.2 Device Nomenclature

      246
  • 8.2 Documentation Support

    247
  • 8.3 Related Links

    248
  • 8.4 Community Resources

    248
  • 8.5 Trademarks

    248
  • 8.6 Electrostatic Discharge Caution

    248
  • 8.7 Glossary

    248
• 9 Mechanical Packaging and Orderable Information

  249
  • 9.1 Thermal Data for ZWT Package

    249
  • 9.2 Packaging Information

    249