数据表 (TMDSCNCD28M36)目录1 Device Summary11.1 Features11.2 Applications21.3 Description21.4 Functional Block Diagram3Table of Contents42 Revision History53 Device Overview63.1 Device Characteristics73.2 Memory Maps103.2.1 Control Subsystem Memory Map103.2.2 Master Subsystem Memory Map153.3 Master Subsystem213.3.1 Cortex-M3 CPU213.3.2 Cortex-M3 DMA and NVIC233.3.3 Cortex-M3 Interrupts233.3.4 Cortex-M3 Vector Table263.3.5 Cortex-M3 Local Peripherals263.3.6 Cortex-M3 Local Memory263.3.7 Cortex-M3 Accessing Shared Resources and Analog Peripherals273.4 Control Subsystem273.4.1 C28x CPU/FPU/VCU293.4.2 C28x Core Hardware Built-In Self-Test293.4.3 C28x Peripheral Interrupt Expansion293.4.4 C28x Direct Memory Access303.4.5 C28x Local Peripherals313.4.6 C28x Local Memory313.4.7 C28x Accessing Shared Resources and Analog Peripherals313.5 Analog Subsystem323.5.1 ADC1323.5.2 ADC2323.5.3 Analog Comparator + DAC343.5.4 Analog Common Interface Bus343.6 Master Subsystem NMIs353.7 Control Subsystem NMIs353.8 Resets373.8.1 Cortex-M3 Resets373.8.2 C28x Resets393.8.3 Analog Subsystem and Shared Resources Resets393.8.4 Device Boot Sequence393.9 Internal Voltage Regulation and Power-On-Reset Functionality423.9.1 Analog Subsystem's Internal 1.8-V VREG423.9.2 Digital Subsystem's Internal 1.2-V VREG443.9.3 Analog and Digital Subsystems' Power-On-Reset Functionality443.9.4 Connecting ARS and XRS Pins443.10 Input Clocks and PLLs453.10.1 Internal Oscillator (Zero-Pin)453.10.2 Crystal Oscillator/Resonator (Pins X1/X2 and VSSOSC)463.10.3 External Oscillators (Pins X1, VSSOSC, XCLKIN)463.10.4 Main PLL463.10.5 USB PLL513.11 Master Subsystem Clocking553.11.1 Cortex-M3 Run Mode583.11.2 Cortex-M3 Sleep Mode583.11.3 Cortex-M3 Deep Sleep Mode593.12 Control Subsystem Clocking603.12.1 C28x Normal Mode603.12.2 C28x IDLE Mode603.12.3 C28x STANDBY Mode623.13 Analog Subsystem Clocking633.14 Shared Resources Clocking633.15 Loss of Input Clock (NMI Watchdog Function)633.16 GPIOs and Other Pins653.16.1 GPIO_MUX1653.16.2 GPIO_MUX2813.16.3 AIO_MUX1833.16.4 AIO_MUX2843.17 Emulation/JTAG853.18 Code Security Module883.18.1 Functional Description883.19 µCRC Module893.19.1 Functional Description893.19.2 CRC Polynomials893.19.3 CRC Calculation Procedure893.19.4 CRC Calculation for Data Stored In Secure Memory904 Terminal Description914.1 Terminal Assignments914.2 Terminal Functions965 Device Operating Conditions1235.1 Absolute Maximum Ratings1235.2 Handling Ratings1235.3 Recommended Operating Conditions1245.4 Electrical Characteristics1256 Electrical Specifications1266.1 Current Consumption1266.2 Thermal Design Considerations1306.3 Timing Parameter Symbology1316.3.1 General Notes on Timing Parameters1316.3.2 Test Load Circuit1316.4 Clock Frequencies, Requirements, and Characteristics1326.4.1 Input Clock Frequency and Timing Requirements, PLL Lock Times1326.4.2 Internal Clock Frequencies1336.4.3 Output Clock Frequency and Switching Characteristics1346.5 Power Sequencing1356.5.1 Changing the Frequency of the Main PLL1376.5.2 Power Management and Supervisory Circuit Solutions1386.6 Flash Timing – Master Subsystem1396.7 Flash Timing – Control Subsystem1426.8 GPIO Electrical Data and Timing1456.8.1 GPIO - Output Timing1456.8.2 GPIO - Input Timing1466.8.3 Sampling Window Width for Input Signals1476.8.4 Low-Power Mode Wakeup Timing1486.9 External Interrupt Electrical Data and Timing1537 Peripheral Information and Timings1547.1 Analog and Shared Peripherals1547.1.1 Analog-to-Digital Converter1547.1.1.1 Sample Mode1547.1.1.2 Start-of-Conversion Triggers1567.1.1.3 Analog Inputs1567.1.1.4 ADC Result Registers and EOC Interrupts1567.1.1.5 ADC Electrical Data and Timing1577.1.2 Comparator + DAC Units1587.1.2.1 On-Chip Comparator and DAC Electrical Data and Timing1607.1.3 Interprocessor Communications1617.1.4 External Peripheral Interface1637.1.4.1 EPI General-Purpose Mode1657.1.4.2 EPI SDRAM Mode1687.1.4.3 EPI Host Bus Mode1707.1.4.4 EPI Electrical Data and Timing1847.2 Master Subsystem Peripherals1907.2.1 Synchronous Serial Interface1907.2.1.1 Bit Rate Generation1907.2.1.2 Transmit FIFO1927.2.1.3 Receive FIFO1927.2.1.4 Interrupts1927.2.1.5 Frame Formats1937.2.2 Universal Asynchronous Receiver/Transmitter1947.2.2.1 Baud-Rate Generation1947.2.2.2 Transmit and Receive Logic1967.2.2.3 Data Transmission and Reception1967.2.2.4 Interrupts1977.2.3 Cortex-M3 Inter-Integrated Circuit1987.2.3.1 Functional Overview1987.2.3.2 Available Speed Modes1987.2.3.3 I2C Electrical Data and Timing2007.2.4 Cortex-M3 Controller Area Network2017.2.4.1 Functional Overview2017.2.5 Cortex-M3 Universal Serial Bus Controller2037.2.5.1 Functional Description2037.2.6 Cortex-M3 Ethernet Media Access Controller2057.2.6.1 Functional Overview2057.2.6.2 MII Signals2077.2.6.3 EMAC Electrical Data and Timing2087.2.6.4 MDIO Electrical Data and Timing2107.3 Control Subsystem Peripherals2117.3.1 High-Resolution PWM and Enhanced PWM Modules2117.3.1.1 HRPWM Electrical Data and Timing2147.3.1.2 ePWM Electrical Data and Timing2147.3.2 Enhanced Capture Module2167.3.2.1 eCAP Electrical Data and Timing2167.3.3 Enhanced Quadrature Encoder Pulse Module2187.3.3.1 eQEP Electrical Data and Timing2187.3.4 C28x Inter-Integrated Circuit Module2207.3.4.1 Functional Overview2227.3.4.2 Clock Generation2227.3.4.3 I2C Electrical Data and Timing2227.3.5 C28x Serial Communications Interface2237.3.5.1 Architecture2257.3.5.2 Multiprocessor and Asynchronous Communication Modes2257.3.6 C28x Serial Peripheral Interface2267.3.6.1 Functional Overview2287.3.6.2 SPI Electrical Data and Timing2287.3.7 C28x Multichannel Buffered Serial Port2367.3.7.1 McBSP Electrical Data and Timing2398 Device and Documentation Support2468.1 Device Support2468.1.1 Development Support2468.1.2 Device Nomenclature2468.2 Documentation Support2478.3 Related Links2488.4 Community Resources2488.5 Trademarks2488.6 Electrostatic Discharge Caution2488.7 Glossary2489 Mechanical Packaging and Orderable Information2499.1 Thermal Data for ZWT Package2499.2 Packaging Information249文件大小: 2.1 MB页数: 253Language: English打开用户手册