用户手册 — Texas Instruments SM320C6455-EP

目录

• Table of Contents

  3
• 1 Features

  7
  • 1.1 ZTZ/GTZ BGA Package (Bottom View)

    8
  • 1.2 Description

    8
  • 1.3  Functional Block Diagram

    10
• 2 Device Overview

  11
  • 2.1 Device Characteristics

    11
  • 2.2 CPU (DSP Core) Description

    12
  • 2.3 Memory Map Summary

    15
  • 2.4 Boot Sequence

    17
    • 2.4.1 Boot Modes Supported

      17
    • 2.4.2 2nd-Level Bootloaders

      19
  • 2.5 Pin Assignments

    20
    • 2.5.1 Pin Map

      20
  • 2.6 Signal Groups Description

    24
  • 2.7 Terminal Functions

    30
  • 2.8 Development

    55
    • 2.8.1 Development Support

      55
    • 2.8.2 Device Support

      55
      • 2.8.2.1  Device and Development-Support Tool Nomenclature

        55
      • 2.8.2.2  Documentation Support

        56
• 3 Device Configuration

  59
  • 3.1 Device Configuration at Device Reset

    59
  • 3.2 Peripheral Configuration at Device Reset

    61
  • 3.3 Peripheral Selection After Device Reset

    63
  • 3.4 Device State Control Registers

    65
    • 3.4.1 Peripheral Lock Register Description

      66
    • 3.4.2 Peripheral Configuration Register 0 Description

      67
    • 3.4.3 Peripheral Configuration Register 1 Description

      69
    • 3.4.4 Peripheral Status Registers Description

      70
    • 3.4.5 EMAC Configuration Register (EMACCFG) Description

      73
    • 3.4.6 Emulator Buffer Powerdown Register (EMUBUFPD) Description

      74
  • 3.5 Device Status Register Description

    75
  • 3.6 JTAG ID (JTAGID) Register Description

    77
  • 3.7 Pullup/Pulldown Resistors

    78
  • 3.8 Configuration Examples

    78
• 4 System Interconnect

  81
  • 4.1 Internal Buses, Bridges, and Switch Fabrics

    81
  • 4.2 Data Switch Fabric Connections

    82
  • 4.3 Configuration Switch Fabric

    84
  • 4.4 Bus Priorities

    86
• 5 C64x+ Megamodule

  87
  • 5.1 Memory Architecture

    87
  • 5.2 Memory Protection

    90
  • 5.3 Bandwidth Management

    90
  • 5.4 Power-Down Control

    91
  • 5.5 Megamodule Resets

    91
  • 5.6 Megamodule Revision

    92
  • 5.7 C64x+ Megamodule Register Description(s)

    93
• 6 Device Operating Conditions

  101
  • 6.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)

    101
  • 6.2 Recommended Operating Conditions

    101
  • 6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)

    103
• 7 C64x+ Peripheral Information and Electrical Specifications

  105
  • 7.1 Parameter Information

    105
    • 7.1.1  3.3-V Signal Transition Levels

      105
    • 7.1.2  3.3-V Signal Transition Rates

      105
    • 7.1.3  Timing Parameters and Board Routing Analysis

      106
  • 7.2 Recommended Clock and Control Signal Transition Behavior

    107
  • 7.3 Power Supplies

    107
    • 7.3.1 Power-Supply Sequencing

      107
    • 7.3.2 Power-Supply Decoupling

      107
    • 7.3.3 Power-Down Operation

      107
    • 7.3.4 Preserving Boundary-Scan Functionality on RGMII and DDR2 Memory Pins

      108
  • 7.4 Enhanced Direct Memory Access (EDMA3) Controller

    109
    • 7.4.1 EDMA3 Device-Specific Information

      110
    • 7.4.2 EDMA3 Channel Synchronization Events

      110
    • 7.4.3 EDMA3 Peripheral Register Description(s)

      111
  • 7.5 Interrupts

    124
    • 7.5.1 Interrupt Sources and Interrupt Controller

      124
    • 7.5.2  External Interrupts Electrical Data/Timing

      127
  • 7.6 Reset Controller

    128
    • 7.6.1 Power-on Reset (POR Pin)

      128
    • 7.6.2 Warm Reset (RESET Pin)

      129
    • 7.6.3 Max Reset

      130
    • 7.6.4 System Reset

      130
    • 7.6.5 CPU Reset

      130
    • 7.6.6 Reset Priority

      131
    • 7.6.7 Reset Controller Register

      132
      • 7.6.7.1 Reset Type Status Register Description

        132
    • 7.6.8 Reset Electrical Data/Timing

      133
  • 7.7 PLL1 and PLL1 Controller

    136
    • 7.7.1 PLL1 Controller Device-Specific Information

      137
      • 7.7.1.1 Internal Clocks and Maximum Operating Frequencies

        137
      • 7.7.1.2 PLL1 Controller Operating Modes

        138
      • 7.7.1.3 PLL1 Stabilization, Lock, and Reset Times

        138
    • 7.7.2 PLL1 Controller Memory Map

      139
    • 7.7.3 PLL1 Controller Register Descriptions

      140
      • 7.7.3.1 PLL1 Control Register

        140
      • 7.7.3.2 PLL Multiplier Control Register

        141
      • 7.7.3.3 PLL Pre-Divider Control Register

        142
      • 7.7.3.4 PLL Controller Divider 4 Register

        143
      • 7.7.3.5 PLL Controller Divider 5 Register

        144
      • 7.7.3.6 PLL Controller Command Register

        145
      • 7.7.3.7 PLL Controller Status Register

        146
      • 7.7.3.8 PLL Controller Clock Align Control Register

        147
      • 7.7.3.9 PLLDIV Ratio Change Status Register

        148
      • 7.7.3.10 SYSCLK Status Register

        149
    • 7.7.4 PLL1 Controller Input and Output Clock Electrical Data/Timing

      150
  • 7.8 PLL2 and PLL2 Controller

    151
    • 7.8.1 PLL2 Controller Device-Specific Information

      152
      • 7.8.1.1 Internal Clocks and Maximum Operating Frequencies

        152
      • 7.8.1.2 PLL2 Controller Operating Modes

        152
    • 7.8.2 PLL2 Controller Memory Map

      153
    • 7.8.3 PLL2 Controller Register Descriptions

      153
      • 7.8.3.1 PLL Controller Divider 1 Register

        154
      • 7.8.3.2 PLL Controller Command Register

        155
      • 7.8.3.3 PLL Controller Status Register

        156
      • 7.8.3.4 PLL Controller Clock Align Control Register

        156
      • 7.8.3.5 PLLDIV Ratio Change Status Register

        157
      • 7.8.3.6 SYSCLK Status Register

        158
    • 7.8.4 PLL2 Controller Input Clock Electrical Data/Timing

      159
  • 7.9 DDR2 Memory Controller

    160
    • 7.9.1 DDR2 Memory Controller Device-Specific Information

      160
    • 7.9.2 DDR2 Memory Controller Peripheral Register Description(s)

      161
    • 7.9.3 DDR2 Memory Controller Electrical Data/Timing

      161
  • 7.10 External Memory Interface A (EMIFA)

    162
    • 7.10.1 EMIFA Device-Specific Information

      162
    • 7.10.2 EMIFA Peripheral Register Description(s)

      163
    • 7.10.3 EMIFA Electrical Data/Timing

      164
      • 7.10.3.1  Asynchronous Memory Timing

        165
      • 7.10.3.2  Programmable Synchronous Interface Timing

        168
    • 7.10.4 HOLD/HOLDA Timing

      171
    • 7.10.5 BUSREQ Timing

      172
  • 7.11 I2C Peripheral

    173
    • 7.11.1 I2C Device-Specific Information

      173
    • 7.11.2 I2C Peripheral Register Description(s)

      175
    • 7.11.3 I2C Electrical Data/Timing

      176
      • 7.11.3.1  Inter-Integrated Circuits (I2C) Timing

        176
  • 7.12 Host-Port Interface (HPI) Peripheral

    179
    • 7.12.1 HPI Device-Specific Information

      179
    • 7.12.2 HPI Peripheral Register Description(s)

      179
    • 7.12.3 HPI Electrical Data/Timing

      180
  • 7.13 Multichannel Buffered Serial Port (McBSP)

    190
    • 7.13.1 McBSP Device-Specific Information

      191
      • 7.13.1.1 McBSP Peripheral Register Description(s)

        191
    • 7.13.2 McBSP Electrical Data/Timing

      193
      • 7.13.2.1  Multichannel Buffered Serial Port (McBSP) Timing

        193
  • 7.14 Ethernet MAC (EMAC)

    200
    • 7.14.1 EMAC Device-Specific Information

      201
    • 7.14.2 EMAC Peripheral Register Description(s)

      204
    • 7.14.3 EMAC Electrical Data/Timing

      208
      • 7.14.3.1  EMAC MII and GMII Electrical Data/Timing

        208
      • 7.14.3.2 EMAC RMII Electrical Data/Timing

        211
      • 7.14.3.3 EMAC RGMII Electrical Data/Timing

        213
    • 7.14.4  Management Data Input/Output (MDIO)

      216
      • 7.14.4.1 MDIO Device-Specific Information

        216
      • 7.14.4.2 MDIO Peripheral Register Description(s)

        216
      • 7.14.4.3 MDIO Electrical Data/Timing

        217
  • 7.15 Timers

    218
    • 7.15.1 Timers Device-Specific Information

      218
    • 7.15.2 Timers Peripheral Register Description(s)

      218
    • 7.15.3 Timers Electrical Data/Timing

      219
  • 7.16 Enhanced Viterbi-Decoder Coprocessor (VCP2)

    220
    • 7.16.1 VCP2 Device-Specific Information

      220
    • 7.16.2 VCP2 Peripheral Register Description(s)

      220
  • 7.17 Enhanced Turbo Decoder Coprocessor (TCP2)

    221
    • 7.17.1 TCP2 Device-Specific Information

      221
    • 7.17.2 TCP2 Peripheral Register Description(s)

      222
  • 7.18 Peripheral Component Interconnect (PCI)

    223
    • 7.18.1 PCI Device-Specific Information

      223
    • 7.18.2 PCI Peripheral Register Description(s)

      224
    • 7.18.3 PCI Electrical Data/Timing

      229
  • 7.19 UTOPIA

    230
    • 7.19.1 UTOPIA Device-Specific Information

      230
    • 7.19.2 UTOPIA Peripheral Register Description(s)

      230
    • 7.19.3 UTOPIA Electrical Data/Timing

      231
  • 7.20 Serial RapidIO (SRIO) Port

    234
    • 7.20.1 Serial RapidIO Device-Specific Information

      234
    • 7.20.2 Serial RapidIO Peripheral Register Description(s)

      234
    • 7.20.3 Serial RapidIO Electrical Data/Timing

      244
  • 7.21 General-Purpose Input/Output (GPIO)

    246
    • 7.21.1 GPIO Device-Specific Information

      246
    • 7.21.2 GPIO Peripheral Register Description(s)

      246
    • 7.21.3 GPIO Electrical Data/Timing

      247
  • 7.22 Emulation Features and Capability

    248
    • 7.22.1 Advanced Event Triggering (AET)

      248
    • 7.22.2 Trace

      248
    • 7.22.3 IEEE 1149.1 JTAG

      249
      • 7.22.3.1 JTAG Device-Specific Information

        249
    • 7.22.4 JTAG Peripheral Register Description(s)

      249
    • 7.22.5 JTAG Electrical Data/Timing

      249
• Revision History

  250
• 8 Mechanical Data

  251
  • 8.1 Thermal Data

    251
  • 8.2 Packaging Information

    251