用户手册 — Texas Instruments TMS320C2XX

目录

• Read This First

  3
• Contents

  12
• Figures

  19
• Tables

  22
• Examples

  24
• Cautions

  25
• Introduction

  26
  • TMS320 Family

    27
    • History, Development, and Advantages of TMS320 DSPs

      27
    • Typical Applications for the TMS320 Family

      29
  • TMS320C2xx Generation

    30
  • Key Features of the TMS320C2xx

    31
• Architectural Overview

  33
  • ’C2xx Bus Structure

    35
  • Central Processing Unit

    37
    • Central Arithmetic Logic Unit (CALU) and Accumulator

      37
    • Scaling Shifters

      37
    • Multiplier

      38
    • Auxiliary Register Arithmetic Unit (ARAU) and Auxiliary Registers

      38
  • Memory and I/O Spaces

    39
    • Dual-Access On-Chip RAM

      39
    • Single-Access On-Chip Program/Data RAM

      40
    • Factory-Masked On-Chip ROM

      40
    • Flash Memory

      41
  • Program Control

    42
  • On-Chip Peripherals

    43
    • Clock Generator

      43
    • CLKOUT1-Pin Control (CLK) Register

      43
    • Hardware Timer

      43
    • Software-Programmable Wait-State Generator

      43
    • General-Purpose I/O Pins

      44
    • Serial Ports

      44
  • Scanning-Logic Circuitry

    45
• Central Processing Unit

  46
  • Input Scaling Section

    48
  • Multiplication Section

    50
    • Multiplier

      50
    • Product-Scaling Shifter

      51
  • Central Arithmetic Logic Section

    53
    • Central Arithmetic Logic Unit (CALU)

      54
    • Accumulator

      54
    • Output Data-Scaling Shifter

      56
  • Auxiliary Register Arithmetic Unit (ARAU)

    57
    • ARAU and Auxiliary Register Functions

      58
  • Status Registers ST0 and ST1

    60
• Memory and I/O Spaces

  63
  • Overview of the Memory and I/O Spaces

    64
    • Pins for Interfacing to External Memory and I/O Spaces

      65
  • Program Memory

    67
    • Interfacing With External Program Memory

      67
  • Local Data Memory

    69
    • Data Page 0 Address Map

      70
    • Interfacing With External Local Data Memory

      71
  • Global Data Memory

    73
    • Interfacing With External Global Data Memory

      74
  • Boot Loader

    76
    • Choosing an EPROM

      76
    • Connecting the EPROM to the Processor

      77
    • Programming the EPROM

      78
    • Enabling the Boot Loader

      79
    • Boot Loader Execution

      80
    • Boot Loader Program

      83
  • I/O Space

    85
    • Accessing I/O Space

      87
  • Direct Memory Access Using the HOLD Operation

    89
    • HOLD During Reset

      91
  • Device-Specific Information

    93
    • TMS320C203 Address Maps and Memory Configuration

      93
    • TMS320C204 Address Maps and Memory Configuration

      96
• Program Control

  100
  • Program-Address Generation

    101
    • Program Counter (PC)

      102
    • Stack

      103
    • Micro Stack (MSTACK)

      105
  • Pipeline Operation

    106
  • Branches, Calls, and Returns

    107
    • Unconditional Branches

      107
    • Unconditional Calls

      107
    • Unconditional Returns

      108
  • Conditional Branches, Calls, and Returns

    109
    • Using Multiple Conditions

      109
    • Stabilization of Conditions

      110
    • Conditional Branches

      110
    • Conditional Calls

      111
    • Conditional Returns

      111
  • Repeating a Single Instruction

    113
  • Interrupts

    114
    • Interrupt Operation: Three Phases

      114
    • Interrupt Table

      115
    • Maskable Interrupts

      117
    • Interrupt Flag Register (IFR)

      119
    • Interrupt Mask Register (IMR)

      121
    • Interrupt Control Register (ICR)

      123
    • Nonmaskable Interrupts

      126
    • Interrupt Service Routines (ISRs)

      128
    • Interrupt Latency

      129
  • Reset Operation

    132
  • Power-Down Mode

    135
    • Normal Termination of Power-Down Mode

      135
    • Termination of Power-Down During a HOLD Operation

      136
• Addressing Modes

  137
  • Immediate Addressing Mode

    138
    • Examples of Immediate Addressing

      138
  • Direct Addressing Mode

    140
    • Using Direct Addressing Mode

      142
    • Examples of Direct Addressing

      142
  • Indirect Addressing Mode

    145
    • Current Auxiliary Register

      145
    • Indirect Addressing Options

      145
    • Next Auxiliary Register

      147
    • Indirect Addressing Opcode Format

      148
    • Examples of Indirect Addressing

      151
    • Modifying Auxiliary Register Content

      153
• Assembly Language Instructions

  154
  • Instruction Set Summary

    155
  • How To Use the Instruction Descriptions

    165
    • Syntax

      165
    • Operands

      167
    • Opcode

      167
    • Execution

      168
    • Status Bits

      168
    • Description

      168
    • Words

      169
    • Cycles

      169
    • Examples

      171
  • Instruction Descriptions

    173
    • ABS

      174
    • ABS

      175
    • ADD

      176
    • ADD

      177
    • ADD

      178
    • ADD

      179
    • ADDC

      180
    • ADDC

      181
    • ADDS

      182
    • ADDS

      183
    • ADDT

      184
    • ADDT

      185
    • ADRK

      186
    • AND

      187
    • AND

      188
    • AND

      189
    • APAC

      190
    • APAC

      191
    • B

      192
    • BACC

      193
    • BANZ

      194
    • BANZ

      195
    • BCND

      196
    • BCND

      197
    • BIT

      198
    • BIT

      199
    • BITT

      200
    • BITT

      201
    • BLDD

      202
    • BLDD

      203
    • BLDD

      204
    • BLDD

      205
    • BLDD

      206
    • BLPD

      207
    • BLPD

      208
    • BLPD

      209
    • BLPD

      210
    • CALA

      211
    • CALL

      212
    • CC

      213
    • CC

      214
    • CLRC

      215
    • CLRC

      216
    • CMPL

      217
    • CMPR

      218
    • DMOV

      219
    • DMOV

      220
    • IDLE

      221
    • IN

      222
    • IN

      223
    • INTR

      224
    • LACC

      225
    • LACC

      226
    • LACC

      227
    • LACL

      228
    • LACL

      229
    • LACL

      230
    • LACT

      231
    • LACT

      232
    • LAR

      233
    • LAR

      234
    • LAR

      235
    • LDP

      236
    • LDP

      237
    • LPH

      238
    • LPH

      239
    • LST

      240
    • LST

      241
    • LST

      242
    • LST

      243
    • LT

      244
    • LT

      245
    • LTA

      246
    • LTA

      247
    • LTD

      248
    • LTD

      249
    • LTD

      250
    • LTP

      251
    • LTP

      252
    • LTS

      253
    • LTS

      254
    • MAC

      255
    • MAC

      256
    • MAC

      257
    • MAC

      258
    • MACD

      259
    • MACD

      260
    • MACD

      261
    • MACD

      262
    • MACD

      263
    • MAR

      264
    • MAR

      265
    • MPY

      266
    • MPY

      267
    • MPY

      268
    • MPYA

      269
    • MPYA

      270
    • MPYS

      271
    • MPYS

      272
    • MPYU

      273
    • MPYU

      274
    • NEG

      275
    • NEG

      276
    • NMI

      277
    • NOP

      278
    • NORM

      279
    • NORM

      280
    • NORM

      281
    • OR

      282
    • OR

      283
    • OR

      284
    • OUT

      285
    • OUT

      286
    • PAC

      287
    • POP

      288
    • POP

      289
    • POPD

      290
    • POPD

      291
    • PSHD

      292
    • PSHD

      293
    • PUSH

      294
    • RET

      295
    • RETC

      296
    • ROL

      297
    • ROR

      298
    • RPT

      299
    • RPT

      300
    • SACH

      301
    • SACH

      302
    • SACL

      303
    • SACL

      304
    • SAR

      305
    • SAR

      306
    • SBRK

      307
    • SETC

      308
    • SETC

      309
    • SFL

      310
    • SFR

      311
    • SFR

      312
    • SPAC

      313
    • SPH

      314
    • SPH

      315
    • SPL

      316
    • SPL

      317
    • SPLK

      318
    • SPLK

      319
    • SPM

      320
    • SQRA

      321
    • SQRA

      322
    • SQRS

      323
    • SQRS

      324
    • SST

      325
    • SST

      326
    • SUB

      327
    • SUB

      328
    • SUB

      329
    • SUB

      330
    • SUBB

      331
    • SUBB

      332
    • SUBC

      333
    • SUBC

      334
    • SUBS

      335
    • SUBS

      336
    • SUBT

      337
    • SUBT

      338
    • TBLR

      339
    • TBLR

      340
    • TBLR

      341
    • TBLW

      342
    • TBLW

      343
    • TBLW

      344
    • TRAP

      345
    • XOR

      346
    • XOR

      347
    • XOR

      348
    • ZALR

      349
    • ZALR

      350
• On-Chip Peripherals

  351
  • Control of On-Chip Peripherals

    352
  • Clock Generator

    354
    • Clock Generator Options

      355
  • CLKOUT1-Pin Control (CLK) Register

    357
  • Timer

    358
    • Timer Operation

      359
    • Timer Control Register (TCR)

      360
    • Timer Counter Register (TIM) and Timer Period Register (PRD)

      362
    • Setting the Timer Interrupt Rate

      363
    • The Timer at Hardware Reset

      363
  • Wait-State Generator

    364
    • Generating Wait States With the READY Signal

      364
    • Generating Wait States With the ’C2xx Wait-State Generator

      364
  • General-Purpose I/O Pins

    367
    • Input Pin BIO

      367
    • Output Pin XF

      368
    • Input/Output Pins IO0, IO1, IO2, and IO3

      368
• Synchronous Serial Port

  369
  • Overview of the Synchronous Serial Port

    370
  • Components and Basic Operation

    371
    • Signals

      371
    • FIFO Buffers and Registers

      373
    • Interrupts

      374
    • Basic Operation

      374
  • Controlling and Resetting the Port

    376
    • Selecting a Mode of Operation (Bit 1 of the SSPCR)

      380
    • Selecting Transmit Clock Source and Transmit Frame Sync Source (Bits 2 and 3 of the SSPCR)

      380
    • Resetting the Synchronous Serial Port (Bits 4 and 5 of the SSPCR)

      381
    • Using Transmit and Receive Interrupts (Bits 8–11 of the SSPCR)

      381
  • Managing the Contents of the FIFO Buffers

    383
  • Transmitter Operation

    384
    • Burst Mode Transmission With Internal Frame Sync (FSM = 1, TXM = 1)

      384
    • Burst Mode Transmission With External Frame Sync (FSM = 1, TXM = 0)

      386
    • Continuous Mode Transmission With Internal Frame Sync (FSM = 0, TXM = 1)

      388
    • Continuous Mode Transmission with External Frame Sync (FSM=0, TXM=0)

      390
  • Receiver Operation

    392
    • Burst Mode Reception

      392
    • Continuous Mode Reception

      393
  • Troubleshooting

    395
    • Test Bits

      395
    • Burst Mode Error Conditions

      397
    • Continuous Mode Error Conditions

      397
• Asynchronous Serial Port

  399
  • Overview of the Asynchronous Serial Port

    400
  • Components and Basic Operation

    401
    • Signals

      401
    • Baud-Rate Generator

      402
    • Registers

      402
    • Interrupts

      403
    • Basic Operation

      404
  • Controlling and Resetting the Port

    405
    • Asynchronous Serial Port Control Register (ASPCR)

      405
    • I/O Status Register (IOSR)

      408
    • Baud-Rate Divisor Register (BRD)

      411
    • Using Automatic Baud-Rate Detection

      412
    • Using I/O Pins IO3, IO2, IO1, and IO0

      413
    • Using Interrupts

      415
  • Transmitter Operation

    417
  • Receiver Operation

    418
• TMS320C209

  419
  • ’C209 Versus Other ’C2xx Devices

    420
    • What Is the Same

      420
    • What Is Different

      420
    • Where to Find the Information You Need About the TMS320C209

      421
  • ’C209 Memory and I/O Spaces

    423
  • ’C209 Interrupts

    428
    • ’C209 Interrupt Registers

      429
    • IACK Pin

      431
  • ’C209 On-Chip Peripherals

    432
    • ’C209 Clock Generator Options

      432
    • ’C209 Timer Control Register (TCR)

      433
    • ’C209 Wait-State Generator

      434
• Register Summary

  436
  • A.1 Addresses and Reset Values

    437
  • A.2 Register Descriptions

    439
• TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison

  450
  • B.1 Using the Instruction Set Comparison Table

    451
    • B.1.1 An Example of a Table Entry

      451
    • B.1.2 Symbols and Acronyms Used in the Table

      452
  • B.2 Enhanced Instructions

    454
  • B.3 Instruction Set Comparison Table

    455
• Program Examples

  486
  • C.1 About These Program Examples

    487
  • C.2 Shared Program Code

    490
  • C.3 Task-Specific Program Code

    493
  • C.4 Introduction to Generating Boot Loader Code

    508
• Submitting ROM Codes to TI

  510
• Design Considerations for Using XDS510 Emulator

  513
  • E.1 Designing Your Target System’s Emulator Connector (14-Pin Header)

    514
  • E.2 Bus Protocol

    516
  • E.3 Emulator Cable Pod

    517
  • E.4 Emulator Cable Pod Signal Timing

    518
  • E.5 Emulation Timing Calculations

    519
  • E.6 Connections Between the Emulator and the Target System

    522
    • E.6.1 Buffering Signals

      522
    • E.6.2 Using a Target-System Clock

      524
    • E.6.3 Configuring Multiple Processors

      525
  • E.7 Physical Dimensions for the 14-Pin Emulator Connector

    526
  • E.8 Emulation Design Considerations

    528
    • E.8.1 Using Scan Path Linkers

      528
    • E.8.2 Emulation Timing Calculations for a Scan Path Linker (SPL)

      530
    • E.8.3 Using Emulation Pins

      532
    • E.8.4 Performing Diagnostic Applications

      536
• Glossary

  538
• Index

  564