用户手册 — Texas Instruments TMS320C6454

目录

• 1 TMS320C6454 Fixed-Point Digital Signal Processor

  1
  • 1.1 Features

    1
  • 1.1.1 ZTZ/GTZ BGA Package (Bottom View)

    2
  • 1.2 Description

    2
  • 1.3  Functional Block Diagram

    4
• Table of Contents

  5
• 2 Device Overview

  6
  • 2.1 Device Characteristics

    6
  • 2.2 CPU (DSP Core) Description

    7
  • 2.3 Memory Map Summary

    10
  • 2.4 Boot Sequence

    12
    • 2.4.1 Boot Modes Supported

      12
    • 2.4.2 2nd-Level Bootloaders

      13
  • 2.5 Pin Assignments

    14
    • 2.5.1 Pin Map

      14
  • 2.6 Signal Groups Description

    18
  • 2.7 Terminal Functions

    24
  • 2.8 Development

    47
    • 2.8.1 Development Support

      47
    • 2.8.2 Device Support

      47
• 3 Device Configuration

  50
  • 3.1 Device Configuration at Device Reset

    50
  • 3.2 Peripheral Configuration at Device Reset

    52
  • 3.3 Peripheral Selection After Device Reset

    53
  • 3.4 Device State Control Registers

    55
    • 3.4.1 Peripheral Lock Register Description

      56
    • 3.4.2 Peripheral Configuration Register 0 Description

      57
    • 3.4.3 Peripheral Configuration Register 1 Description

      59
    • 3.4.4 Peripheral Status Registers Description

      60
    • 3.4.5 EMAC Configuration Register (EMACCFG) Description

      63
    • 3.4.6 Emulator Buffer Powerdown Register (EMUBUFPD) Description

      64
  • 3.5 Device Status Register Description

    65
  • 3.6 JTAG ID (JTAGID) Register Description

    67
  • 3.7 Pullup/Pulldown Resistors

    67
  • 3.8 Configuration Examples

    69
• 4 System Interconnect

  71
  • 4.1 Internal Buses, Bridges, and Switch Fabrics

    71
  • 4.2 Data Switch Fabric Connections

    72
  • 4.3 Configuration Switch Fabric

    74
  • 4.4 Priority Allocation

    76
• 5 C64x+ Megamodule

  77
  • 5.1 Memory Architecture

    77
  • 5.2 Memory Protection

    80
  • 5.3 Bandwidth Management

    80
  • 5.4 Power-Down Control

    81
  • 5.5 Megamodule Resets

    81
  • 5.6 Megamodule Revision

    82
  • 5.7 C64x+ Megamodule Register Description(s)

    83
• 6 Device Operating Conditions

  90
  • 6.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)

    90
  • 6.2 Recommended Operating Conditions

    90
  • 6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)

    92
• 7 C64x+ Peripheral Information and Electrical Specifications

  94
  • 7.1 Parameter Information

    94
    • 7.1.1  3.3-V Signal Transition Levels

      94
    • 7.1.2  3.3-V Signal Transition Rates

      94
    • 7.1.3  Timing Parameters and Board Routing Analysis

      95
  • 7.2 Recommended Clock and Control Signal Transition Behavior

    96
  • 7.3 Power Supplies

    96
    • 7.3.1 Power-Supply Sequencing

      96
    • 7.3.2 Power-Supply Decoupling

      96
    • 7.3.3 Power-Down Operation

      96
    • 7.3.4 Preserving Boundary-Scan Functionality on RGMII and DDR2 Memory Pins

      97
  • 7.4 Enhanced Direct Memory Access (EDMA3) Controller

    98
    • 7.4.1 EDMA3 Device-Specific Information

      98
    • 7.4.2 EDMA3 Channel Synchronization Events

      99
    • 7.4.3 EDMA3 Peripheral Register Description(s)

      100
  • 7.5 Interrupts

    112
    • 7.5.1 Interrupt Sources and Interrupt Controller

      112
    • 7.5.2  External Interrupts Electrical Data/Timing

      115
  • 7.6 Reset Controller

    116
    • 7.6.1 Power-on Reset (POR Pin)

      116
    • 7.6.2 Warm Reset (RESET Pin)

      117
    • 7.6.3 System Reset

      118
    • 7.6.4 CPU Reset

      118
    • 7.6.5 Reset Priority

      119
    • 7.6.6 Reset Controller Register

      119
    • 7.6.7 Reset Electrical Data/Timing

      120
  • 7.7 PLL1 and PLL1 Controller

    123
    • 7.7.1 PLL1 Controller Device-Specific Information

      124
    • 7.7.2 PLL1 Controller Memory Map

      126
    • 7.7.3 PLL1 Controller Register Descriptions

      127
    • 7.7.4 PLL1 Controller Input and Output Clock Electrical Data/Timing

      137
  • 7.8 PLL2 and PLL2 Controller

    138
    • 7.8.1 PLL2 Controller Device-Specific Information

      139
    • 7.8.2 PLL2 Controller Memory Map

      140
    • 7.8.3 PLL2 Controller Register Descriptions

      140
    • 7.8.4 PLL2 Controller Input Clock Electrical Data/Timing

      146
  • 7.9 DDR2 Memory Controller

    147
    • 7.9.1 DDR2 Memory Controller Device-Specific Information

      147
    • 7.9.2 DDR2 Memory Controller Peripheral Register Description(s)

      148
    • 7.9.3 DDR2 Memory Controller Electrical Data/Timing

      148
  • 7.10 External Memory Interface A (EMIFA)

    149
    • 7.10.1 EMIFA Device-Specific Information

      149
    • 7.10.2 EMIFA Peripheral Register Description(s)

      150
    • 7.10.3 EMIFA Electrical Data/Timing

      151
    • 7.10.4 HOLD/HOLDA Timing

      158
    • 7.10.5 BUSREQ Timing

      159
  • 7.11 I2C Peripheral

    160
    • 7.11.1 I2C Device-Specific Information

      160
    • 7.11.2 I2C Peripheral Register Description(s)

      162
    • 7.11.3 I2C Electrical Data/Timing

      163
  • 7.12 Host-Port Interface (HPI) Peripheral

    166
    • 7.12.1 HPI Device-Specific Information

      166
    • 7.12.2 HPI Peripheral Register Description(s)

      166
    • 7.12.3 HPI Electrical Data/Timing

      167
  • 7.13 Multichannel Buffered Serial Port (McBSP)

    177
    • 7.13.1 McBSP Device-Specific Information

      178
    • 7.13.2 McBSP Electrical Data/Timing

      180
  • 7.14 Ethernet MAC (EMAC)

    187
    • 7.14.1 EMAC Device-Specific Information

      188
    • 7.14.2 EMAC Peripheral Register Description(s)

      191
    • 7.14.3 EMAC Electrical Data/Timing

      195
    • 7.14.4  Management Data Input/Output (MDIO)

      203
  • 7.15 Timers

    205
    • 7.15.1 Timers Device-Specific Information

      205
    • 7.15.2 Timers Peripheral Register Description(s)

      205
    • 7.15.3 Timers Electrical Data/Timing

      206
  • 7.16 Peripheral Component Interconnect (PCI)

    207
    • 7.16.1 PCI Device-Specific Information

      207
    • 7.16.2 PCI Peripheral Register Description(s)

      208
    • 7.16.3 PCI Electrical Data/Timing

      213
  • 7.17 General-Purpose Input/Output (GPIO)

    214
    • 7.17.1 GPIO Device-Specific Information

      214
    • 7.17.2 GPIO Peripheral Register Description(s)

      214
    • 7.17.3 GPIO Electrical Data/Timing

      215
  • 7.18 IEEE 1149.1 JTAG

    216
    • 7.18.1 JTAG Device-Specific Information

      216
    • 7.18.2 JTAG Peripheral Register Description(s)

      216
    • 7.18.3 JTAG Electrical Data/Timing

      216
• 8 Mechanical Data

  217
  • 8.1 Thermal Data

    217
  • 8.2 Packaging Information

    217
• Revision History

  218