Samsung M395T5160QZ4 M395T5160QZ4-CF760 Benutzerhandbuch
Produktcode
M395T5160QZ4-CF760
Rev. 1.4 May 2009
FBDIMM
DDR2 SDRAM
30 of 42
[ Table 14 ] Differential Receiver Input Specifications
Notes :
1. Specified at the package pins into a timing and voltage compliant test setup. Note that signal levels at the pad will be lower than at the pin.
2. Single-ended voltages below that value that are simultaneously detected on D+ and D-are interpreted as the Electrical Idle condition. Worst-case mar-
1. Specified at the package pins into a timing and voltage compliant test setup. Note that signal levels at the pad will be lower than at the pin.
2. Single-ended voltages below that value that are simultaneously detected on D+ and D-are interpreted as the Electrical Idle condition. Worst-case mar-
gins are determined for the case with transmitter using small voltage swing.
3. Multiple lanes need to detect the El condition before the device can act upon the El detection.
4. Specified at the package pins into a timing and voltage compliance test setup.
5. The single-pulse mask provides sufficient symbol energy for reliable RX reception. Each symbol must comply with both the single-pulse mask and the
4. Specified at the package pins into a timing and voltage compliance test setup.
5. The single-pulse mask provides sufficient symbol energy for reliable RX reception. Each symbol must comply with both the single-pulse mask and the
cumulative eyemask.
6. The relative amplitude ratio limit between adjacent symbols prevents excessive intersymbol interference in the RX. Each symbol must comply with the
peak amplitude ratio with regard to both the preceding and subsequent symbols.
7. This number does not include the effects of SSC or reference clock jitter.
8. This number includes setup and hold of the RX sampling flop.
9. Defined as the dual-dirac deterministic timing error.
10. Allows for 15 mV DC offset between transmit and receive devices.
8. This number includes setup and hold of the RX sampling flop.
9. Defined as the dual-dirac deterministic timing error.
10. Allows for 15 mV DC offset between transmit and receive devices.
Parameter
Symbol
Values
Units
Comments
MIN
MAX
Differential peak-to-peak input voltage for large voltage swing
V
RX-DIFFp-p
170
TBD
mV
EQ 5, Note1
Maximum single-ended voltage in El condition
V
RX-IDLE-SE
75
mV
2,3
Maximum single-ended voltage in Ei condition (DC only)
V
RX-IDLE-SE-DC
50
mV
2,3
Maximum peak-to-peak differential voltage in El condition
V
RX-IDLE-DIFFp-p
65
mV
3
Single-ended voltage (w.r.t. V
SS
) on D+/D-
V
RX-SE
-300
900
mV
4
Single-pulse peak differential input voltage
V
RX-DIFF-PULSE
85
mV
4,5
Amplitude ratio between adjacent symbols
V
RX-DIFF-ADJ-RATIO
TBD
4,6
Maximum RX inherent timing error, 3.2 and 4.0 Gb/x
T
RX-TJ-MAX
0.4
UI
4,7,8
Maximum RX inherent deterministic timing error, 3.2 and 4.8 Gb/s
T
RX-TJ-MAX4.8
TBD
UI
4,7,8
Single-pulse width as zero-voltage crossing
V
RX-DJ-DD
0.3
UI
4,7,8,9
Single-pulse width at minimum-level crossing
V
RX-DJ-DD-4.8
TBD
UI
4,7,8,9
Differential RX input rise/fall time
T
RX-PW-ZC
0.55
UI
4,5
Common mode of the input voltage
T
RX-PW-ML
0.2
UI
4.5
Differential RX output rise/fall time
T
RX-RISE
T
RX-FALL
50
ps
20~80% voltage
Common mode of input voltage
V
RX-CM
120
400
mV
EQ 6, Note1, 10
AC peak-to-peak common mode of input voltage
V
RX-CM-ACp-p
270
mV
EQ 7, Note 1
Ratio of V
RX-CM-ACp-p
to minimum V
RX-DIFFp-p
V
RX-CM-EH-RATOP
45
%
11
Differential return loss
RL
RX-DIFF
9
dB
1GHz-2.4 GHz, Note 12
Common mode return loss
RL
RX-CM
6
dB
1GHz-2.4 GHz, Note 12
RX termination impedance
R
RX
41
55
Ω
13
D+/D- RX Impedance difference
R
RX-MATCH-DC
4
%
EQ 8
Lane-to lane PCB skew at RX
L
RX-PCB-SKEW
6
UI
Lane-to-lane skew at the receiver
that must be tolerated. Note 14
Minimum RX drift tolerance
T
RX-DRIFT
400
ps
15
Minim data tracking 3dB bandwidth
F
TRK
0.2
MHz
16
Electrical idle entry detect time
T
EI-ENTRY-DETECT
60
ns
17
Electrical idle exit detect time
T
EI-EXIT-DETECT
30
ns
Bit Error Ratio
BER
10
-12
18