Datenbogen (LF80550KF0878M)Inhaltsverzeichnis1 Introduction111.1 Terminology121.2 Reference Documents141.3 State of Data142 Electrical Specifications152.1 Front Side Bus and GTLREF152.1.1 Front Side Bus Clock and Processor Clocking152.1.2 Front Side Bus Clock Select (BSEL[1:0])162.1.3 Phase Lock Loop (PLL) Power and Filter172.2 Voltage Identification (VID)172.3 Reserved, Unused, and TESTHI Pins202.4 Mixing Processors202.5 Front Side Bus Signal Groups212.6 GTL+ Asynchronous Signals and AGTL + Asynchronous Signals222.7 Test Access Port (TAP) Connection232.8 Absolute Maximum and Minimum Ratings232.9 Processor DC Specifications242.9.1 Flexible Motherboard (FMB) Guidelines242.9.2 Vcc Overshoot Specification283 Mechanical Specifications333.1 Package Mechanical Drawing333.2 Processor Component Keepout Zones363.3 Package Loading Specifications363.4 Package Handling Guidelines373.5 Package Insertion Specifications373.6 Processor Mass Specifications373.7 Processor Materials373.8 Processor Markings383.9 Processor Pin-Out Coordinates394 Pin Listing414.1 Dual-Core Intel Xeon Processor 7000 Series Pin Assignments414.1.1 Pin Listing by Pin Name414.1.2 Pin Listing by Pin Number505 Signal Definitions595.1 Signal Definitions596 Thermal Specifications676.1 Package Thermal Specifications676.1.1 Thermal Specifications676.1.2 Thermal Metrology706.2 Processor Thermal Features706.2.1 Thermal Monitor706.2.2 On-Demand Mode716.2.3 PROCHOT# Signal Pin716.2.4 FORCEPR# Signal Pin726.2.5 THERMTRIP# Signal Pin726.2.6 Tcontrol and Fan Speed Reduction726.2.7 Thermal Diode727 Features737.1 Power-On Configuration Options737.2 Clock Control and Low Power States737.2.1 Normal State737.2.2 HALT Power Down State747.2.3 Stop-Grant State747.2.4 HALT/Grant Snoop State757.2.5 Enhanced HALT Powerdown State757.3 Enhanced Intel SpeedStep® Technology767.4 System Management Bus (SMBus) Interface767.4.1 Processor Information ROM (PIROM)777.4.2 Scratch EEPROM807.4.3 PIROM and Scratch EEPROM Supported SMBus Transactions807.4.4 SMBus Thermal Sensor817.4.5 Thermal Sensor Supported SMBus Transactions817.4.6 SMBus Thermal Sensor Registers847.4.7 SMBus Thermal Sensor Alert Interrupt877.4.8 SMBus Device Addressing887.4.9 Managing Data in the PIROM898 Boxed Processor Specifications978.1 Introduction978.2 Mechanical Specifications988.2.1 Boxed Processor Heatsink Dimensions988.2.2 Boxed Processor Heatsink Weight1048.2.3 Boxed Processor Retention Mechanism and Heatsink Supports1048.3 Thermal Specifications1058.3.1 Boxed Processor Cooling Requirements1058.3.2 Boxed Processor Contents1059 Debug Tools Specifications1079.1 Logic Analyzer Interface (LAI)1079.1.1 Mechanical Considerations1079.1.2 Electrical Considerations107Größe: 2,63 MBSeiten: 108Language: EnglishHandbuch öffnen