Emerson ATCA-9305 User Manual
Cavium Processor Complex:
Headers and Connectors
3-15
Console Serial Ports (optional)
Connectors P6 (processor P1) and P5 (processor P2) access the CN5860 processors for Engi-
neering debug use only. The supported baud rates for these ports operate at 9600, 14400,
19200, 38400, 57600, and 115200 bps. (The default rate is 115200 bps.)
neering debug use only. The supported baud rates for these ports operate at 9600, 14400,
19200, 38400, 57600, and 115200 bps. (The default rate is 115200 bps.)
Table 3-8:
CN5860 Processor Debug Headers
5
P2_ETDO
P1_ETDO
6
ground
ground
7
P2_TMS
P1_TMS
8
ground
ground
9
P2_TCK
P1_TCK
10
ground
ground
11
P2_EJTAG_RST
P1_EJTAG_RST
12
key (pin not installed)
key (pin not installed)
13
P2_EJTAG_DINT
P1_EJTAG_DINT
14
P2_COP_PWR (3.3V)
P1_COP_PWR (3.3V)
Pin:
P6:
P5:
1
no connect
no connect
2
P1_SER1_RXD
P2_SER1_RXD
3
P1_SER1_TXD
P2_SER1_TXD
4
no connect
no connect
5
signal ground
signal ground
6-7
shield
signal ground
Pin:
J1 (processor 2):
J15 (processor 1):
(continued)