Epson ARM720T User Manual

Modes, privileged 8-10
Monitor mode 9-4, 9-12, 9-13
Multi-ICE 9-8

O

Operating modes

Operating state

P

Page tables 7-5
Permission faults 7-15, 7-20
Pipeline

Privileged instructions 8-10
Privileged modes 8-10
Processor

Program status registers

control bits 2-8
mode bit values 2-9
reserved bits 2-9

Programming EmbeddedICE-RT 
9-7
Programming watchpoints 9-38
PROT bits 9-35
Protocol converter 9-2
Public instructions 9-20

R

Range 9-36, 9-37, 9-38, 9-43, 9-44
RANGE bit 9-36
Read data bus

Register

cache test 11-3
control value 9-36
debug status 9-42
fault address 7-16
fault status 7-16
MMU test 11-8
test 11-1
test state 11-3
translation table base 7-4

Cache Operations Register 3-7
Control Register 3-4
debug communications chan-

debug control

Fault Address Register 3-7
Fault Status Register 3-6
ID Register 3-3
instruction 9-20, 9-21, 9-22, 

register 13, process identifier 

register

Test Registers 3-9
Thumb 2-6
TLB Operations Register 3-7
Translation Table Base Regis-

ter 3-5, 7-4

Registers, debug

address mask 9-37
BYPASS 9-21
bypass 9-22
control mask 9-33, 9-35
control value 9-33, 9-35
data mask 9-33
data value 9-33
EmbeddedICE-RT 9-24

accessing 9-17, 9-24
debug status 9-26

ID 9-22
instruction 9-20, 9-21, 9-22, 

scan path select 9-22, 9-23
scan path select register 9-20
status 9-41
status register 9-26
test data 9-22
watchpoint address mask 9-33
watchpoint address value 9-33

Reset

Response encoding 6-10
RESTART

9-29
Return address calculation 9-32
Returned TCK, 

See RTCK

RTCK 9-8
RUN-TEST/IDLE state 9-21, 9-29

S

Scan

input cells 9-20
output cells 9-20
path 9-20
paths 9-17

Scan cells 9-21, 9-24
Scan chain

Scan chain 1 9-17, 9-24, 9-25, 9-27, 
9-28, 9-29, 9-30
Scan chain 1 cells 9-25
Scan chain 2 9-17, 9-24, 9-33
Scan chains 9-17

Scan path select register 9-20, 
9-22, 9-23
SCAN_N 9-20, 9-23, 9-24
Section

descriptor 7-8
references, translating 7-10

SHIFT-DR 9-19, 9-20, 9-21, 9-25
SHIFT-IR 9-23
Signals

AMBA interface A-1
coprocessor interface A-2
debugger A-4
ETM interface A-5
JTAG A-3
miscellaneous A-7

Single-step core operation 9-20
SIZE 6-7
SIZE bits 9-35
Slave

Small page references, translating 
7-13
Software breakpoints 9-36, 9-37

Software Interrupt 2-13
Software interrupt 2-13
SPSR (Saved Processor Status 
Register) 2-8

State

CAPTURE-DR 9-20, 9-21
processor 9-27
SHIFT-DR 9-19, 9-20, 9-21, 

UPDATE-DR 9-20, 9-21
UPDATE-IR 9-23

Subpages 7-14
Supervisor mode 2-4