Nxp Semiconductors UM10310 User Manual
UM10310_1
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 01 — 1 December 2008
112 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
5. If both the EIEE (IEN1.7) bit and the EA (IEN0.7) bit are logic 1s, wait for the Data
EEPROM interrupt then read/poll the EEIF (DEECON.7) bit until it is set to logic 1. If
EIEE or EA is logic 0, the interrupt is disabled and only polling is enabled. When EEIF
is logic 1, the operation is complete and row is filled with the DEEDAT pattern.
EIEE or EA is logic 0, the interrupt is disabled and only polling is enabled. When EEIF
is logic 1, the operation is complete and row is filled with the DEEDAT pattern.
6. Poll EWERR0 flag. If EWERR0 (DEECON.1) bit is logic 1, it means BOD EEPROM
occurred (V
DD
<2.4V) during program or erase and the previous operation may not be
correct.
17.7 Data EEPROM Block Fill
The Data EEPROM array can be filled with a predetermined data pattern via polling or
interrupt:
interrupt:
1. Write to DEECON with ECTL1/ECTL0 (DEECON[5:4]) = ‘11’and EWERR1/EWERR0
(DEECON[2:1]) =’00’. Set bit EADR8 = 1.
2. Write the fill pattern to the DEEDAT register.
3. Write any address to DEEADR. Note that the entire address is ignored in a block fill
operation.
4. Poll EWERR1 flag. If EWERR1 (DEECON.2) bit is logic 1, BOD EEPROM occurred
(V
DD
<2.4V) and Data EEPROM program is blocked.
5. If both the EIEE (IEN1.7) bit and the EA (IEN0.7) bit are logic 1s, wait for the Data
EEPROM interrupt then read/poll the EEIF (DEECON.7) bit until it is set to logic 1. If
EIEE or EA is logic 0, the interrupt is disabled and only polling is enabled. When EEIF
is logic 1, the operation is complete.
EIEE or EA is logic 0, the interrupt is disabled and only polling is enabled. When EEIF
is logic 1, the operation is complete.
6. Poll EWERR0 flag. If EWERR0 (DEECON.1) bit is logic 1, it means BOD EEPROM
occurred (V
DD
<2.4V) during program or erase and the previous operation may not be
correct.
18. Flash memory
18.1 General description
The P89LPC9321 Flash memory provides in-circuit electrical erasure and programming.
The Flash can be read and written as bytes. The Sector and Page Erase functions can
erase any Flash sector (1 kB) or page (64 bytes). The Chip Erase operation will erase the
entire program memory. Five Flash programming methods are available. On-chip erase
and write timing generation contribute to a user-friendly programming interface. The
P89LPC9321 Flash reliably stores memory contents even after 100,000 erase and
program cycles. The cell is designed to optimize the erase and programming
mechanisms. P89LPC9321 uses V
The Flash can be read and written as bytes. The Sector and Page Erase functions can
erase any Flash sector (1 kB) or page (64 bytes). The Chip Erase operation will erase the
entire program memory. Five Flash programming methods are available. On-chip erase
and write timing generation contribute to a user-friendly programming interface. The
P89LPC9321 Flash reliably stores memory contents even after 100,000 erase and
program cycles. The cell is designed to optimize the erase and programming
mechanisms. P89LPC9321 uses V
DD
as the supply voltage to perform the Program/Erase
algorithms. When voltage supply is lower than 2.4V, the BOD FLASH is tripped and flash
erase/program is blocked.
erase/program is blocked.
18.2 Features
•
Parallel programming with industry-standard commercial programmers
•
In-Circuit serial Programming (ICP) with industry-standard commercial programmers.
•
IAP-Lite allows individual and multiple bytes of code memory to be used for data
storage and programmed under control of the end application.
storage and programmed under control of the end application.