Nxp Semiconductors UM10310 User Manual
UM10310_1
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 01 — 1 December 2008
113 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
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Internal fixed boot ROM, containing low-level In-Application Programming (IAP)
routines that can be called from the end application (in addition to IAP-Lite).
routines that can be called from the end application (in addition to IAP-Lite).
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Default serial loader providing In-System Programming (ISP) via the serial port,
located in upper end of user program memory.
located in upper end of user program memory.
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Boot vector allows user provided Flash loader code to reside anywhere in the Flash
memory space, providing flexibility to the user.
memory space, providing flexibility to the user.
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Programming and erase over the full operating voltage range
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Read/Programming/Erase using ISP, IAP or IAP-Lite
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Any flash program operation in 2 ms (4 ms for erase/program)
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Programmable security for the code in the Flash for each sector
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> 100,000 typical erase/program cycles for each byte
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10-year minimum data retention
18.3 Flash programming and erase
The P89LPC9321 program memory consists 1 kB sectors. Each sector can be further
divided into 64-byte pages. In addition to sector erase and page erase, a 64-byte page
register is included which allows from 1 to 64 bytes of a given page to be programmed at
the same time, substantially reducing overall programming time. Five methods of
programming this device are available.
divided into 64-byte pages. In addition to sector erase and page erase, a 64-byte page
register is included which allows from 1 to 64 bytes of a given page to be programmed at
the same time, substantially reducing overall programming time. Five methods of
programming this device are available.
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Parallel programming with industry-standard commercial programmers.
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In-Circuit serial Programming (ICP) with industry-standard commercial programmers.
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IAP-Lite allows individual and multiple bytes of code memory to be used for data
storage and programmed under control of the end application.
storage and programmed under control of the end application.
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Internal fixed boot ROM, containing low-level In-Application Programming (IAP)
routines that can be called from the end application (in addition to IAP-Lite).
routines that can be called from the end application (in addition to IAP-Lite).
•
A factory-provided default serial loader, located in upper end of user program
memory, providing In-System Programming (ISP) via the serial port.
memory, providing In-System Programming (ISP) via the serial port.
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Note: Flash erase/program will be blocked if BOD FLASH is detected (V
DD
<2.4 V).
18.4 Using Flash as data storage: IAP-Lite
The Flash code memory array of this device supports IAP-Lite in addition to standard IAP
functions. Any byte in a non-secured sector of the code memory array may be read using
the MOVC instruction and thus is suitable for use as non-volatile data storage. IAP-Lite
provides an erase-program function that makes it easy for one or more bytes within a
page to be erased and programmed in a single operation without the need to erase or
program any other bytes in the page. IAP-Lite is performed in the application under the
control of the microcontroller’s firmware using four SFRs and an internal 64-byte ‘page
register’ to facilitate erasing and programing within unsecured sectors. These SFRs are:
functions. Any byte in a non-secured sector of the code memory array may be read using
the MOVC instruction and thus is suitable for use as non-volatile data storage. IAP-Lite
provides an erase-program function that makes it easy for one or more bytes within a
page to be erased and programmed in a single operation without the need to erase or
program any other bytes in the page. IAP-Lite is performed in the application under the
control of the microcontroller’s firmware using four SFRs and an internal 64-byte ‘page
register’ to facilitate erasing and programing within unsecured sectors. These SFRs are:
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FMCON (Flash Control Register). When read, this is the status register. When written,
this is a command register. Note that the status bits are cleared to logic 0s when the
command is written.
this is a command register. Note that the status bits are cleared to logic 0s when the
command is written.
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FMADRL, FMADRH (Flash memory address low, Flash memory address high). Used
to specify the byte address within the page register or specify the page within user
code memory
to specify the byte address within the page register or specify the page within user
code memory