Nxp Semiconductors UM10237 User Manual
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
733 of 792
NXP Semiconductors
UM10237
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
There are situations when the GPDMA asserts the lock for source transfers followed by
destination transfers. This is possible when internal conditions in the GPDMA permit it to
perform a source fetch followed by a destination drain back-to-back.
destination transfers. This is possible when internal conditions in the GPDMA permit it to
perform a source fetch followed by a destination drain back-to-back.
6.2.8 Flow control and transfer type
lists the bit values of the three flow control and transfer type bits.
7.
Address generation
Address generation can be either incrementing or non-incrementing (address wrapping is
not supported). Bursts do not cross the 1 kB address boundary.
not supported). Bursts do not cross the 1 kB address boundary.
8.
Scatter/Gather
Scatter/gather is supported through the use of linked lists. This means that the source and
destination areas do not have to occupy contiguous areas in memory. Where
scatter/gather is not required the DMACCxLLI Register must be set to 0.
destination areas do not have to occupy contiguous areas in memory. Where
scatter/gather is not required the DMACCxLLI Register must be set to 0.
The source and destination data areas are defined by a series of linked lists. Each Linked
List Item (LLI) controls the transfer of one block of data, and then optionally loads another
LLI to continue the DMA operation, or stops the DMA stream. The first LLI is programmed
into the GPDMA.
List Item (LLI) controls the transfer of one block of data, and then optionally loads another
LLI to continue the DMA operation, or stops the DMA stream. The first LLI is programmed
into the GPDMA.
The data to be transferred described by a LLI (referred to as the packet of data) usually
requires one or more DMA bursts (to each of the source and destination).
requires one or more DMA bursts (to each of the source and destination).
8.1 Linked List Items
A Linked List Item (LLI) consists of four words. These words are organized in the following
order:
order:
1. DMACCxSrcAddr.
2. DMACCxDestAddr.
3. DMACCxLLI.
4. DMACCxControl.
Note: The DMACCxConfiguration DMA channel Configuration Register is not part of the
linked list item.
linked list item.
Table 676. Flow control and transfer type bits
Bit Value Transfer Type
Controller
000
Memory to memory.
DMA
001
Memory to peripheral.
DMA
010
Peripheral to memory.
DMA
011
Source peripheral to destination peripheral.
DMA
100
Source peripheral to destination peripheral.
Destination peripheral.
101
Memory to peripheral.
Peripheral.
110
Peripheral to memory.
Peripheral.
111
Source peripheral to destination peripheral.
Source peripheral.