Nxp Semiconductors UM10237 User Manual
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
735 of 792
NXP Semiconductors
UM10237
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
•
Source start address 0x0A200.
•
Destination address set to the destination peripheral address.
•
Transfer width, word (32 bit).
•
Transfer size, 3 072 bytes (0XC00).
•
Source and destination burst sizes, 16 transfers.
•
Next LLI address, 0x20010.
The second LLI, stored at 0x20010 , describes the next block of data to be transferred:
•
Source start address 0x0B200.
•
Destination address set to the destination peripheral address.
•
Transfer width, word (32 bit).
•
Transfer size, 3 072 bytes (0xC00).
•
Source and destination burst sizes, 16 transfers.
•
Next LLI address, 0x20020.
A chain of descriptors is built up, each one pointing to the next in the series. To initialize
the DMA stream, the first LLI, 0x20000, is programmed into the GPDMA. When the first
packet of data has been transferred the next LLI is automatically loaded.
the DMA stream, the first LLI, 0x20000, is programmed into the GPDMA. When the first
packet of data has been transferred the next LLI is automatically loaded.
The final LLI is stored at 0x20070 and contains:
•
Source start address 0x11200.
•
Destination address set to the destination peripheral address.
•
Transfer width, word (32 bit).
•
Transfer size, 3 072 bytes (0xC00).
•
Source and destination burst sizes, 16 transfers.
•
Next LLI address, 0x0.
Because the next LLI address is set to zero, this is the last descriptor, and the DMA
channel is disabled after transferring the last item of data. The channel is probably set to
generate an interrupt at this point to indicate to the ARM processor that the channel can
be reprogrammed.
channel is disabled after transferring the last item of data. The channel is probably set to
generate an interrupt at this point to indicate to the ARM processor that the channel can
be reprogrammed.
9.
Interrupt requests
Interrupt requests can be generated when an AHB error is encountered, or at the end of a
transfer (terminal count) after all the data corresponding to the current LLI has been
transferred to the destination. The interrupts can be masked by programming bits in the
relevant DMACCxControl and DMACCxConfiguration Channel Registers. Interrupt status
registers are provided which group the interrupt requests from all the DMA channels prior
to interrupt masking (DMACRawIntTCStatus and DMACRawIntErrorStatus), and after
interrupt masking (DMACIntTCStatus and DMACIntErrorStatus). The DMACIntStatus
Register combines both the DMACIntTCStatus and DMACIntErrorStatus requests into a
single register to enable the source of an interrupt to be quickly found. Writing to the
DMACIntTCClear or the DMACIntErrClr Registers with a bit set HIGH enables selective
clearing of interrupts.
transfer (terminal count) after all the data corresponding to the current LLI has been
transferred to the destination. The interrupts can be masked by programming bits in the
relevant DMACCxControl and DMACCxConfiguration Channel Registers. Interrupt status
registers are provided which group the interrupt requests from all the DMA channels prior
to interrupt masking (DMACRawIntTCStatus and DMACRawIntErrorStatus), and after
interrupt masking (DMACIntTCStatus and DMACIntErrorStatus). The DMACIntStatus
Register combines both the DMACIntTCStatus and DMACIntErrorStatus requests into a
single register to enable the source of an interrupt to be quickly found. Writing to the
DMACIntTCClear or the DMACIntErrClr Registers with a bit set HIGH enables selective
clearing of interrupts.