Jameco Electronics 3000 User Manual
User’s Manual
191
With NRZ and NRZI encoding all transitions occur on bit-cell boundaries and the data
should be sampled in the middle of the bit cell. If a transition occurs after the expected bit-
cell boundary (but before the midpoint) the DPLL needs to lengthen the count to line up
the bit-cell boundaries. This corresponds to the “add one” and “add two” regions shown. If
a transition occurs before the bit cell boundary (but after the midpoint) the DPLL needs to
shorten the count to line up the bit-cell boundaries. This corresponds to the “subtract one”
and “subtract two” regions shown. The DPLL makes no adjustment if the bit-cell bound-
aries are lined up within one count of the divide-by-sixteen counter. The regions that
adjust the count by two allow the DPLL to synchronize faster to the data stream when
starting up.
should be sampled in the middle of the bit cell. If a transition occurs after the expected bit-
cell boundary (but before the midpoint) the DPLL needs to lengthen the count to line up
the bit-cell boundaries. This corresponds to the “add one” and “add two” regions shown. If
a transition occurs before the bit cell boundary (but after the midpoint) the DPLL needs to
shorten the count to line up the bit-cell boundaries. This corresponds to the “subtract one”
and “subtract two” regions shown. The DPLL makes no adjustment if the bit-cell bound-
aries are lined up within one count of the divide-by-sixteen counter. The regions that
adjust the count by two allow the DPLL to synchronize faster to the data stream when
starting up.
With Biphase-Level encoding there is a guaranteed “clock” transition at the center of
every bit cell and optional “data” transitions at the bit cell boundaries. The DPLL only
uses the clock transitions to track the bit cell boundaries, by ignoring all transitions occur-
ring outside a window around the center of the bit cell. This window is half a bit-cell wide.
Additionally, because the clock transitions are guaranteed, the DPLL requires that they
always be present. If no transition is found in the window around the center of the bit cell
for two successive bit cells the DPLL is not in lock and immediately enters the search
mode. Search mode assumes that the next transition seen is a clock transition and immedi-
ately synchronizes to this transition. No clock output is provided to the receiver during the
search operation. Decoding Biphase-Level data requires that the data be sampled at either
the quarter or three-quarter point in the bit cell. The DPLL here uses the quarter point to
sample the data.
every bit cell and optional “data” transitions at the bit cell boundaries. The DPLL only
uses the clock transitions to track the bit cell boundaries, by ignoring all transitions occur-
ring outside a window around the center of the bit cell. This window is half a bit-cell wide.
Additionally, because the clock transitions are guaranteed, the DPLL requires that they
always be present. If no transition is found in the window around the center of the bit cell
for two successive bit cells the DPLL is not in lock and immediately enters the search
mode. Search mode assumes that the next transition seen is a clock transition and immedi-
ately synchronizes to this transition. No clock output is provided to the receiver during the
search operation. Decoding Biphase-Level data requires that the data be sampled at either
the quarter or three-quarter point in the bit cell. The DPLL here uses the quarter point to
sample the data.
Biphase-Mark and Biphase space encoding are identical as far as the DPLL is concerned,
and are similar to Biphase-Level. The primary difference is the placement of the clock and
data transitions. With these encodings the clock transitions are at the bit-cell boundary and
the data transitions are at the center of the bit cell, and the DPLL operation is adjusted
accordingly. Decoding Biphase-Mark or Biphase-Space encoding requires that the data be
sampled by both edges of the recovered receive clock.
and are similar to Biphase-Level. The primary difference is the placement of the clock and
data transitions. With these encodings the clock transitions are at the bit-cell boundary and
the data transitions are at the center of the bit cell, and the DPLL operation is adjusted
accordingly. Decoding Biphase-Mark or Biphase-Space encoding requires that the data be
sampled by both edges of the recovered receive clock.
An optional IRDA (Infrared Data Association) -compliant encode and decode function is
available in both asynchronous mode and HDLC mode. The encoder sends an active-High
pulse for a zero and no pulse for a one. In the asynchronous 16x mode this pulse is 3/16ths
of a bit cell wide, while in the asynchronous 8x mode it is 1/8th of a bit cell wide. In
HDLC mode the pulse is 1/4th of a bit cell wide. In all modes the decoder watches for
active-Low pulses, which are stretched to one bit time wide to recreate the normal asyn-
chronous waveform for the receiver. Enabling the IRDA-compliant encode/decode modi-
fies the transmitter in HDLC mode so that there are always two opening Flags transmitted.
available in both asynchronous mode and HDLC mode. The encoder sends an active-High
pulse for a zero and no pulse for a one. In the asynchronous 16x mode this pulse is 3/16ths
of a bit cell wide, while in the asynchronous 8x mode it is 1/8th of a bit cell wide. In
HDLC mode the pulse is 1/4th of a bit cell wide. In all modes the decoder watches for
active-Low pulses, which are stretched to one bit time wide to recreate the normal asyn-
chronous waveform for the receiver. Enabling the IRDA-compliant encode/decode modi-
fies the transmitter in HDLC mode so that there are always two opening Flags transmitted.