Jameco Electronics 3000 User Manual
User’s Manual
193
LD (HL),A
; 6 update the in pointer
IOI LD A,(SCDR) ; 11 get data register port C, clears interrupt request
IPRES ; 4 restore the interrupt priority
; 68 clocks to here
; to level before interrupt took place
; more interrupts could now take place,
; but receiver data is in registers
; now handle the rest of the receiver interrupt routine
LD HL,bufbase ; 6
LD D,0 ; 6
ADD HL,DE ; 2 location to store data
LD (HL),A ; 6 put away the data byte
POP DE ; 7
POP HL ; 7
POP AF ; 7
RET ; 8 from interrupt
; 117 clocks to here
This routine gets the interrupts turned on in about 68 clocks or 3.5 µs at a clock speed of
20 MHz. Although two characters may be handled out of order, this will be invisible to a
higher level routine checking the status of the input buffer because all the interrupts will
be completed before the higher level routine can perform a check on the buffer status.
20 MHz. Although two characters may be handled out of order, this will be invisible to a
higher level routine checking the status of the input buffer because all the interrupts will
be completed before the higher level routine can perform a check on the buffer status.
A typical way to organize the buffers is to have an in-pointer and an out-pointer that incre-
ment through the addresses in the data buffer in a circular manner. The interrupt routine
manipulates the in-pointer and the higher level routine manipulates the out-pointer. If the
in-pointer equals the out-pointer, the buffer is considered full. If the out-pointer plus 1
equals the in-pointer, the buffer is empty. All increments are done in a circular fashion,
most easily accomplished by making the buffer a power of two in length, then anding a
mask after the increment. The actual memory address is the pointer plus a buffer base
address.
ment through the addresses in the data buffer in a circular manner. The interrupt routine
manipulates the in-pointer and the higher level routine manipulates the out-pointer. If the
in-pointer equals the out-pointer, the buffer is considered full. If the out-pointer plus 1
equals the in-pointer, the buffer is empty. All increments are done in a circular fashion,
most easily accomplished by making the buffer a power of two in length, then anding a
mask after the increment. The actual memory address is the pointer plus a buffer base
address.
12.9.1 Controlling an RS-485 Driver and Receiver
RS-485 uses a half-duplex method of communication. One station enables its driver and
sends a message. After the message is complete, the station disables the driver and listens
to the line for a reply. The driver must be enabled before the start bit is sent and not dis-
abled until the stop bit has been sent. The transmitter idle interrupt is normally used to
disable the RS-485 driver and possibly enable the receiver.
sends a message. After the message is complete, the station disables the driver and listens
to the line for a reply. The driver must be enabled before the start bit is sent and not dis-
abled until the stop bit has been sent. The transmitter idle interrupt is normally used to
disable the RS-485 driver and possibly enable the receiver.
12.9.2 Transmitting Dummy Characters
It may be desired to operate the serial transmitter without actually sending any data. “Dummy”
characters are transmitted to pass time or to measure time.
characters are transmitted to pass time or to measure time.
The output of the transmitter may be disconnected from the transmitter output pin by manip-
ulating the control registers for Parallel Port C or D, which are used as output pins. For
example, if Serial Port B is to be temporarily disconnected from its output pin, which is bit
4 of Parallel Port C, this can be done as follows.
ulating the control registers for Parallel Port C or D, which are used as output pins. For
example, if Serial Port B is to be temporarily disconnected from its output pin, which is bit
4 of Parallel Port C, this can be done as follows.
1. Store a "1" in bit 4 of the parallel port data output register to provide the quiescent state
of the drive line.