Nxp Semiconductors LPC2919 User Manual

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

In addition to the two 16 kB TCMs the LPC2917/19 includes two static RAM memories: 
one of 32 kB and one of 16 kB. Both may be used for code and/or data storage. Each 
internal SRAM has its own controller, so both memories can be accessed simultaneously 
from different AHB system bus layers. 

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ARM968E-S processor at 80 MHz maximum

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Multi-layer AHB system bus at 80 MHz with three separate layers

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On-chip memory:

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Two Tightly Coupled Memories (TCM), 16 kB Instruction (ITCM), 16 kB Data TCM 
(DTCM)

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Two separate internal Static RAM (SRAM) instances; 32 kB SRAM and 16 kB 
SRAM

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Up to 768 kB flash-program memory

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Two-channel CAN controller supporting Full-CAN and extensive message filtering

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Two LIN master controllers with full hardware support for LIN communication

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Two 550 UARTs with 16-byte Tx and Rx FIFO depths

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Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep; Tx 
FIFO and Rx FIFO

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Four 32-bit timers each containing four capture-and-compare registers linked to I/Os

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32-bit watchdog with timer change protection, running on safe clock.

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Up to 108 general-purpose I/O pins with programmable pull-up, pull-down or bus 
keeper

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Vectored Interrupt Controller (VIC) with 16 priority levels

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Two 8-channel 10-bit ADCs provide a total of up to 16 analog inputs, with conversion 
times as low as 2.44

μs per channel. Each channel provides a compare function to 

minimize interrupts

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Up to 24 level-sensitive external interrupt pins, including CAN and LIN wake- up 
features

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External Static Memory Controller (SMC) with eight memory banks; up to 32-bit data 
bus; up to 24-bit address bus

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Processor wake-up from power-down via external interrupt pins; CAN or LIN activity

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Flexible Reset Generator Unit (RGU) able to control resets of individual modules

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Flexible Clock-Generation Unit (CGU) able to control clock frequency of individual 
modules

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On-chip very low-power ring oscillator; fixed frequency of 0.4 MHz; always on to 
provide a Safe_Clock source for system monitoring

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On-chip crystal oscillator with operating range from 10 MHz to 50 MHz - max. PLL 
input 15 MHz

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On-chip PLL allows CPU operation up to a maximum CPU rate of 80 MHz

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Generation of up to 10 base clocks

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Seven fractional dividers