Nxp Semiconductors LPC2919 User Manual
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LPC2917_19_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 1.01 — 15 November 2007
5 of 68
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
5.
Block diagram
Fig 1.
LPC2917/19 block diagram
IEEE 1149.1 JTAG TEST and
DEBUG INTERFACE
LPC2917/19
DTCM
16 Kb
ITCM
16 Kb
ARM968E-S
m
s
s
s
s
s
s
s
s
s
Multi-layer AHB
system bus
m = master port
s = slave port
External Static Memory
Controller (SMC)
Embedded
SRAM Memory 32 Kb
SRAM Controller #0
Embedded
FLASH Memory
512/768 Kb
FLASH Memory Controller (FMC)
Embedded
SRAM Memory 16 Kb
SRAM Controller #1
GLOBAL ACCEPTANCE
FILTER
2 Kbyte Static RAM
LIN MASTER 0/1
CAN Controller
0, 1
Vectored Interrupt
Controller (VIC)
AH
B2
VPB
B
ri
dge
AH
B2
D
T
L
B
ri
dge
Modulation and Sampling
Control Subsystem
PWM 0, 1, 2, 3
ADC 1, 2
Timer 0, 1 (MTMR)
AH
B2
VPB
B
ri
dge
Power Clock Reset
Control Subsystem
Power Management Unit (PMU)
Reset Generation Unit (RGU)
Clock Generation Unit (CGU)
AH
B
2
D
T
L
B
ri
dge
s
General Subsystem
Event Router (ER)
System Control Unit (SCU)
Chip Feature ID (CFID)
AH
B
2
V
P
B
B
ri
dge
Peripheral Subsystem
General Purpose IO (GPIO)
0, 1, 2, 3
Timer (TMR)
0, 1, 2, 3
Watchdog Timer (WDT)
UART 0, 1
AH
B2
VPB
Br
id
g
e
SPI 0, 1, 2
s