Intel IXP42X User Manual
Intel
®
IXP42X product line and IXC1100 control plane processors—High-Speed Serial
Interfaces
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM
September 2006
464
Order Number: 252480-006US
, the 'a' denotes the first E1 stream, the 'b' denotes the second E1 stream,
the 2 streams are interlaced byte wise.
Another method of placing E1 stream on this backplane is to process the first entire E1
stream followed by the second complete E2 stream (frame interleaving).
illustrates a method in which 2 T1 frames are placed on a 4.096Mbps
backplane. It can be seen that the first 2 timeslots are unassigned with the exception of
the frame pulse. The first three timeslots of each T1 stream are then placed
(interlaced) in succession on the bus, then 1 unassigned timeslot per T1 stream
present are placed on the bus. Unassigned RX bytes do not pass through the HSS FIFO
(lookup tables give unassigned timeslots).
The HSS can also transmit unassigned timeslots, the value of which is programmable.
The NPE need only supply the contents of the T1 frames, it does not need to transmit
unused timeslots to the HSS. The location of these unassigned timeslots are defined by
the lookup table.
The backplane can contain the 2 T1 streams byte interlaced as shown in
or
the T1 stream can be placed in its entirety first followed by 8 unassigned timeslots
(frame pulse at the last bit of the 32nd timeslot. The second T1 stream then
commences followed by 8 unassigned timeslots. The frame pulse is coincidental with
the last bit in the 32nd timeslot. The second timeslot follows the format of the first
timeslot and together take up the 64 timeslots available. Once again the HSS can be
programmed by the NPE to ignore the 8 unassigned timeslots while taking the frame bit
into account.
17.6.3.3
MVIP Using 8.192-Mbps Backplane
This backplane supports 4 E1 or 4 T1 streams on a single line which require that it
operates at 8.192MHz.
Figure 93.
MVIP, Byte Interleaving Two T1 Streams Onto a 4.096-Mbps Backplane
B4252-02
0
x
x
x
x
x
x
x
x
x
1
2
3
4
5
6
7
6
5
4
3
2
1
0
7
6
7
Xa Xb 0a 0b 1a 1b 2a 2b Xa Xb 3a 3b 4a 4b 5a 5b Xa Xb 6a 6b 7a 7b 8a 8b Xa Xb 9a 9b 10a 10b 11a 11b
Timeslots
Bits
31b
Xa
4.096
MHz clock
Frame pulse
x
x
x
x
x x
0
Unused
timeslots
Frame pulse plus 7 unused bits